fujieqiall.tan.summary

来自「用FPGA实现数字复接?肍PGA实现数字复接」· SUMMARY 代码 · 共 57 行

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Timing Analyzer Summary
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Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : 19.000 ns
From           : c6
To             : djhlatch:m12|sig_save
From Clock     : --
To Clock       : ena
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 13.700 ns
From           : shixusuccessful:m5|count32:u2|lpm_counter:count_5_rtl_0|alt_counter_f10ke:wysi_counter|q[4]
To             : S0
From Clock     : clk
To Clock       : --
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : -9.100 ns
From           : c0
To             : djhlatch:m12|sig_save
From Clock     : --
To Clock       : ena
Failed Paths   : 0

Type           : Clock Setup: 'clk'
Slack          : N/A
Required Time  : None
Actual Time    : Restricted to 125.00 MHz ( period = 8.000 ns )
From           : shixusuccessful:m5|count32:u2|lpm_counter:count_5_rtl_0|alt_counter_f10ke:wysi_counter|q[0]
To             : shixusuccessful:m5|count32:u2|lpm_counter:count_5_rtl_0|alt_counter_f10ke:wysi_counter|q[4]
From Clock     : clk
To Clock       : clk
Failed Paths   : 0

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 0

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