djhlatch.vhd

来自「用FPGA实现数字复接?肍PGA实现数字复接」· VHDL 代码 · 共 22 行

library ieee ;
use ieee.std_logic_1164.all ;

entity djhlatch is
	port(D,ena:in	std_logic;
	ql:out   std_logic
	);
end djhlatch;
architecture behv of djhlatch is
signal sig_save:std_logic;
begin
process(D,ena)
begin
if ena='1' then
sig_save<=d;
end if;
ql<=sig_save;
end process;
end behv;