fujieqiall.sim.talkback.xml
来自「用FPGA实现数字复接?肍PGA实现数字复接」· XML 代码 · 共 129 行
XML
129 行
<!--
This XML file (created on Mon May 22 23:20:41 2006) contains limited information
from the compilation of logic designs using Quartus II software (BUT NOT THE
LOGIC DESIGN FILES) that will be transmitted to Altera Corporation through
operation of the "TalkBack" feature. To enable/disable this feature, run
qtb_install.exe located in your quartus/bin folder. For more information, go
to www.altera.com/products/software/download/dnl-download_license.html
-->
<talkback>
<ver>5.1</ver>
<schema>quartus_version_5.1_build_216.xsd</schema><license>
<nic_id>000c76594cd8</nic_id>
<cdrive_id>7886784f</cdrive_id>
</license>
<tool>
<name>Quartus II</name>
<version>5.1</version>
<build>Build 216</build>
<service_pack_label>2</service_pack_label>
<binary_type>32</binary_type>
<module>quartus_sim.exe</module>
<edition>Web Edition</edition>
<eval>Eval</eval>
<compilation_end_time>Mon May 22 23:20:42 2006</compilation_end_time>
</tool>
<machine>
<os>Windows XP</os>
<cpu>
<proc_count>1</proc_count>
<cpu_freq units="MHz">2019</cpu_freq>
</cpu>
<ram units="MB">224</ram>
</machine>
<top_file>F:/EDA/fujieqiall/fujieqiall</top_file>
<compilation_summary>
<flow_status>Successful - Mon May 22 23:20:41 2006</flow_status>
<simulator_setting_name>fujieqiall</simulator_setting_name>
<top_level_entity_name>fujieqiall</top_level_entity_name>
</compilation_summary>
<compile_id>34111C12</compile_id>
<mep_data>
<command_line>quartus_sim --read_settings_files=on --write_settings_files=off fujieqiall -c fujieqiall</command_line>
</mep_data>
<messages>
<info>Info: Quartus II Simulator was successful. 0 errors, 0 warnings</info>
<info>Info: Elapsed time: 00:00:02</info>
<info>Info: Processing ended: Mon May 22 23:20:41 2006</info>
<info>Info: Number of transitions in simulation is 3257</info>
<info>Info: Simulation coverage is 56.00 %</info>
</messages>
<simulator_settings>
<row>
<option>Simulation mode</option>
<setting>Timing</setting>
<default_value>Timing</default_value>
</row>
<row>
<option>Start time</option>
<setting units="ns">0</setting>
<default_value units="ns">0</default_value>
</row>
<row>
<option>Add pins automatically to simulation output waveforms</option>
<setting>On</setting>
<default_value>On</default_value>
</row>
<row>
<option>Check outputs</option>
<setting>Off</setting>
<default_value>Off</default_value>
</row>
<row>
<option>Report simulation coverage</option>
<setting>On</setting>
<default_value>On</default_value>
</row>
<row>
<option>Detect setup and hold time violations</option>
<setting>Off</setting>
<default_value>Off</default_value>
</row>
<row>
<option>Detect glitches</option>
<setting>Off</setting>
<default_value>Off</default_value>
</row>
<row>
<option>Automatically save/load simulation netlist</option>
<setting>Off</setting>
<default_value>Off</default_value>
</row>
<row>
<option>Disable timing delays in Timing Simulation</option>
<setting>Off</setting>
<default_value>Off</default_value>
</row>
<row>
<option>Generate Signal Activity File</option>
<setting>Off</setting>
<default_value>Off</default_value>
</row>
<row>
<option>Group bus channels in simulation results</option>
<setting>Off</setting>
<default_value>Off</default_value>
</row>
<row>
<option>Preserve fewer signal transitions to reduce memory requirements</option>
<setting>On</setting>
<default_value>On</default_value>
</row>
<row>
<option>Overwrite Waveform Inputs With Simulation Outputs</option>
<setting>On</setting>
</row>
</simulator_settings>
<simulator_summary>
<simulation_start_time>0 ps</simulation_start_time>
<simulation_end_time>1.0 us</simulation_end_time>
<simulation_netlist_size>73 nodes</simulation_netlist_size>
<simulation_coverage> 56.00 %</simulation_coverage>
<total_number_of_transitions>3257</total_number_of_transitions>
<family>FLEX10K</family>
<device>EPF10K10LC84-3</device>
</simulator_summary>
<compile_id>9B33D81E</compile_id>
</talkback>
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