fujieqiall.rpp.talkback.xml

用FPGA实现数字复接?肍PGA实现数字复接

<!--
This XML file (created on Mon May 22 23:11:34 2006) contains limited information
from the compilation of logic designs using Quartus II software (BUT NOT THE
LOGIC DESIGN FILES) that will be transmitted to Altera Corporation through
operation of the "TalkBack" feature.  To enable/disable this feature, run
qtb_install.exe located in your quartus/bin folder.  For more information, go
to www.altera.com/products/software/download/dnl-download_license.html
-->
<talkback>
<ver>5.1</ver>
<schema>quartus_version_5.1_build_216.xsd</schema><license>
	<nic_id>000c76594cd8</nic_id>
	<cdrive_id>7886784f</cdrive_id>
</license>
<tool>
	<name>Quartus II</name>
	<version>5.1</version>
	<build>Build 216</build>
	<service_pack_label>2</service_pack_label>
	<binary_type>32</binary_type>
	<module>quartus_rpp.exe</module>
	<edition>Web Edition</edition>
	<eval>Eval</eval>
	<compilation_end_time>Mon May 22 23:11:34 2006</compilation_end_time>
</tool>
<machine>
	<os>Windows XP</os>
	<cpu>
		<proc_count>1</proc_count>
		<cpu_freq units="MHz">2019</cpu_freq>
	</cpu>
	<ram units="MB">224</ram>
</machine>
<top_file>F:/EDA/fujieqiall/fujieqiall</top_file>
<compilation_summary>
	<flow_status>Successful - Mon May 22 23:10:59 2006</flow_status>
	<quartus_ii_version>5.1 Build 216 03/06/2006 SP 2 SJ Web Edition</quartus_ii_version>
	<revision_name>fujieqiall</revision_name>
	<top_level_entity_name>fujieqiall</top_level_entity_name>
	<family>FLEX10K</family>
	<met_timing_requirements>Yes</met_timing_requirements>
	<total_logic_elements>34 / 576 ( 6 % )</total_logic_elements>
	<total_pins>39 / 59 ( 66 % )</total_pins>
	<total_memory_bits>0 / 6,144 ( 0 % )</total_memory_bits>
	<device>EPF10K10LC84-3</device>
	<timing_models>Final</timing_models>
</compilation_summary>
<compile_id>6E2E331</compile_id>
<mep_data>
	<command_line>quartus_rpp fujieqiall -c fujieqiall --netlist_type=sgate</command_line>
</mep_data>
<software_data>
	<smart_recompile>off</smart_recompile>
</software_data>
<messages>
	<info>Info: Quartus II RTL Viewer, Technology Map Viewer &amp; State Machine Viewer Preprocessor was successful. 0 errors, 0 warnings</info>
	<info>Info: Elapsed time: 00:00:01</info>
	<info>Info: Processing ended: Mon May 22 23:11:34 2006</info>
	<info>Info: Command: quartus_rpp fujieqiall -c fujieqiall --netlist_type=sgate</info>
	<info>Info: Running Quartus II RTL Viewer, Technology Map Viewer &amp; State Machine Viewer Preprocessor</info>
</messages>
<fitter_settings>
	<row>
		<option>Device</option>
		<setting>AUTO</setting>
	</row>
	<row>
		<option>Use smart compilation</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Router Timing Optimization Level</option>
		<setting>Normal</setting>
		<default_value>Normal</default_value>
	</row>
	<row>
		<option>Placement Effort Multiplier</option>
		<setting>1.0</setting>
		<default_value>1.0</default_value>
	</row>
	<row>
		<option>Router Effort Multiplier</option>
		<setting>1.0</setting>
		<default_value>1.0</default_value>
	</row>
	<row>
		<option>Optimize Timing</option>
		<setting>Normal compilation</setting>
		<default_value>Normal compilation</default_value>
	</row>
	<row>
		<option>Optimize IOC Register Placement for Timing</option>
		<setting>On</setting>
		<default_value>On</default_value>
	</row>
	<row>
		<option>Limit to One Fitting Attempt</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Final Placement Optimizations</option>
		<setting>Automatically</setting>
		<default_value>Automatically</default_value>
	</row>
	<row>
		<option>Fitter Aggressive Routability Optimizations</option>
		<setting>Automatically</setting>
		<default_value>Automatically</default_value>
	</row>
	<row>
		<option>Fitter Initial Placement Seed</option>
		<setting>1</setting>
		<default_value>1</default_value>
	</row>
	<row>
		<option>Slow Slew Rate</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Auto Global Memory Control Signals</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Logic Cell Insertion - Individual Logic Cells</option>
		<setting>On</setting>
		<default_value>On</default_value>
	</row>
	<row>
		<option>Logic Cell Insertion - I/Os Fed By Carry or Cascade Chains</option>
		<setting>On</setting>
		<default_value>On</default_value>
	</row>
	<row>
		<option>Fitter Effort</option>
		<setting>Auto Fit</setting>
		<default_value>Auto Fit</default_value>
	</row>
	<row>
		<option>Auto Global Clock</option>
		<setting>On</setting>
		<default_value>On</default_value>
	</row>
	<row>
		<option>Auto Global Output Enable</option>
		<setting>On</setting>
		<default_value>On</default_value>
	</row>
	<row>
		<option>Auto Global Register Control Signals</option>
		<setting>On</setting>
		<default_value>On</default_value>
	</row>
</fitter_settings>
<fitter_device_options>
	<row>
		<option>Enable user-supplied start-up clock (CLKUSR)</option>
		<setting>Off</setting>
	</row>
	<row>
		<option>Enable device-wide reset (DEV_CLRn)</option>
		<setting>Off</setting>
	</row>
	<row>
		<option>Enable device-wide output enable (DEV_OE)</option>
		<setting>Off</setting>
	</row>
	<row>
		<option>Enable INIT_DONE output</option>
		<setting>Off</setting>
	</row>
	<row>
		<option>Configuration scheme</option>
		<setting>Passive Serial</setting>
	</row>
	<row>
		<option>Reserve all unused pins</option>
		<setting>As output driving ground</setting>
	</row>
	<row>
		<option>Base pin-out file on sameframe device</option>
		<setting>Off</setting>
	</row>
</fitter_device_options>
<analysis___synthesis_settings>
	<row>
		<option>Top-level entity name</option>
		<setting>fujieqiall</setting>
		<default_value>fujieqiall</default_value>
	</row>
	<row>
		<option>Family name</option>
		<setting>FLEX10K</setting>
		<default_value>Stratix</default_value>
	</row>
	<row>
		<option>Use smart compilation</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Create Debugging Nodes for IP Cores</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Preserve fewer node names</option>
		<setting>On</setting>
		<default_value>On</default_value>
	</row>
	<row>
		<option>Disable OpenCore Plus hardware evaluation</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Verilog Version</option>
		<setting>Verilog_2001</setting>
		<default_value>Verilog_2001</default_value>
	</row>
	<row>
		<option>VHDL Version</option>
		<setting>VHDL93</setting>
		<default_value>VHDL93</default_value>
	</row>
	<row>
		<option>State Machine Processing</option>
		<setting>Auto</setting>
		<default_value>Auto</default_value>
	</row>
	<row>
		<option>Extract Verilog State Machines</option>
		<setting>On</setting>
		<default_value>On</default_value>
	</row>
	<row>
		<option>Extract VHDL State Machines</option>
		<setting>On</setting>
		<default_value>On</default_value>
	</row>
	<row>
		<option>Add Pass-Through Logic to Inferred RAMs</option>
		<setting>On</setting>
		<default_value>On</default_value>
	</row>
	<row>
		<option>NOT Gate Push-Back</option>
		<setting>On</setting>
		<default_value>On</default_value>
	</row>
	<row>
		<option>Power-Up Don&apos;t Care</option>
		<setting>On</setting>
		<default_value>On</default_value>
	</row>
	<row>
		<option>Remove Redundant Logic Cells</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Remove Duplicate Registers</option>
		<setting>On</setting>
		<default_value>On</default_value>
	</row>
	<row>
		<option>Ignore CARRY Buffers</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Ignore CASCADE Buffers</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Ignore GLOBAL Buffers</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Ignore ROW GLOBAL Buffers</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Ignore LCELL Buffers</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Ignore SOFT Buffers</option>
		<setting>On</setting>
		<default_value>On</default_value>
	</row>
	<row>
		<option>Limit AHDL Integers to 32 Bits</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Auto Implement in ROM</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Optimization Technique -- FLEX 10K/10KE/10KA/ACEX 1K</option>
		<setting>Area</setting>
		<default_value>Area</default_value>
	</row>
	<row>
		<option>Carry Chain Length -- FLEX 10K</option>
		<setting>32</setting>
		<default_value>32</default_value>
	</row>
	<row>
		<option>Cascade Chain Length</option>
		<setting>2</setting>
		<default_value>2</default_value>
	</row>
	<row>
		<option>Auto Carry Chains</option>
		<setting>On</setting>
		<default_value>On</default_value>
	</row>
	<row>
		<option>Auto Open-Drain Pins</option>
		<setting>On</setting>
		<default_value>On</default_value>
	</row>
	<row>
		<option>Remove Duplicate Logic</option>
		<setting>On</setting>
		<default_value>On</default_value>
	</row>
	<row>
		<option>Auto ROM Replacement</option>
		<setting>On</setting>
		<default_value>On</default_value>
	</row>
	<row>
		<option>Auto RAM Replacement</option>
		<setting>On</setting>
		<default_value>On</default_value>
	</row>
	<row>
		<option>Auto Clock Enable Replacement</option>
		<setting>On</setting>
		<default_value>On</default_value>
	</row>
	<row>
		<option>Auto Resource Sharing</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Allow Any RAM Size For Recognition</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Allow Any ROM Size For Recognition</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Ignore translate_off and translate_on Synthesis Directives</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Show Parameter Settings Tables in Synthesis Report</option>
		<setting>On</setting>
		<default_value>On</default_value>
	</row>
	<row>
		<option>HDL message level</option>
		<setting>Level2</setting>
		<default_value>Level2</default_value>
	</row>
</analysis___synthesis_settings>
<assembler_settings>
	<row>
		<option>Use smart compilation</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Generate Serial Vector Format File (.svf) for Target Device</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Generate a JEDEC STAPL Format File (.jam) for Target Device</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Generate an uncompressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device</option>
		<setting>On</setting>
		<default_value>On</default_value>
	</row>
	<row>
		<option>Compression mode</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Clock source for configuration device</option>
		<setting>Internal</setting>
		<default_value>Internal</default_value>
	</row>
	<row>
		<option>Clock frequency of the configuration device</option>
		<setting units="MHz">10</setting>
		<default_value units="MHz">10</default_value>
	</row>
	<row>
		<option>Divide clock frequency by</option>
		<setting>1</setting>
		<default_value>1</default_value>
	</row>
	<row>
		<option>Low-voltage mode</option>
		<setting>On</setting>
		<default_value>On</default_value>
	</row>
	<row>
		<option>JTAG user code for target device</option>
		<setting>7F</setting>
		<default_value>7F</default_value>
	</row>
	<row>
		<option>Configuration device</option>
		<setting>Auto</setting>
		<default_value>Auto</default_value>
	</row>
	<row>
		<option>JTAG user code for configuration device</option>
		<setting>Ffffffff</setting>
		<default_value>Ffffffff</default_value>
	</row>
	<row>
		<option>Configuration device auto user code</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Generate Tabular Text File (.ttf) For Target Device</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Generate Raw Binary File (.rbf) For Target Device</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Generate Hexadecimal (Intel-Format) Output File (.hexout) for Target Device</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Hexadecimal Output File start address</option>
		<setting>0</setting>
		<default_value>0</default_value>
	</row>
	<row>
		<option>Hexadecimal Output File count direction</option>
		<setting>Up</setting>
		<default_value>Up</default_value>
	</row>
	<row>
		<option>Release clears before tri-states</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Auto-restart configuration after error</option>
		<setting>On</setting>
		<default_value>On</default_value>
	</row>
</assembler_settings>
<general_register_statistics>
	<row>
		<statistic>Total registers</statistic>
		<value>8</value>
	</row>
	<row>
		<statistic>Number of registers using Synchronous Clear</statistic>
		<value>0</value>
	</row>
	<row>
		<statistic>Number of registers using Synchronous Load</statistic>
		<value>0</value>
	</row>
	<row>
		<statistic>Number of registers using Asynchronous Clear</statistic>
		<value>0</value>
	</row>
	<row>
		<statistic>Number of registers using Asynchronous Load</statistic>