agc.map.rpt

AGC verilog实现

Analysis & Synthesis report for agc
Thu Dec 01 22:18:31 2011
Quartus II Version 10.0 Build 262 08/18/2010 Service Pack 1 SJ Web Edition


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Analysis & Synthesis Summary
  3. Analysis & Synthesis Settings
  4. Parallel Compilation
  5. Analysis & Synthesis Source Files Read
  6. Analysis & Synthesis Resource Usage Summary
  7. Analysis & Synthesis Resource Utilization by Entity
  8. Analysis & Synthesis IP Cores Summary
  9. User-Specified and Inferred Latches
 10. Logic Cells Representing Combinational Loops
 11. Registers Removed During Synthesis
 12. Removed Registers Triggering Further Register Optimizations
 13. General Register Statistics
 14. Parameter Settings for User Entity Instance: Top-level Entity: |agc
 15. Parameter Settings for User Entity Instance: mymult:mymult|mymult_altfp_mult_3tn:mymult_altfp_mult_3tn_component|lpm_add_sub:exp_add_adder
 16. Parameter Settings for User Entity Instance: mymult:mymult|mymult_altfp_mult_3tn:mymult_altfp_mult_3tn_component|lpm_add_sub:exp_adj_adder
 17. Parameter Settings for User Entity Instance: mymult:mymult|mymult_altfp_mult_3tn:mymult_altfp_mult_3tn_component|lpm_add_sub:exp_bias_subtr
 18. Parameter Settings for User Entity Instance: mymult:mymult|mymult_altfp_mult_3tn:mymult_altfp_mult_3tn_component|lpm_add_sub:man_round_adder
 19. Parameter Settings for User Entity Instance: mymult:mymult|mymult_altfp_mult_3tn:mymult_altfp_mult_3tn_component|lpm_mult:man_product2_mult
 20. lpm_mult Parameter Settings by Entity Instance
 21. Port Connectivity Checks: "mymult:mymult"
 22. Analysis & Synthesis Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2010 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+-------------------------------------------------------------------------------+
; Analysis & Synthesis Summary                                                  ;
+-------------------------------+-----------------------------------------------+
; Analysis & Synthesis Status   ; Successful - Thu Dec 01 22:18:31 2011         ;
; Quartus II Version            ; 10.0 Build 262 08/18/2010 SP 1 SJ Web Edition ;
; Revision Name                 ; agc                                           ;
; Top-level Entity Name         ; agc                                           ;
; Family                        ; Stratix III                                   ;
; Logic utilization             ; N/A                                           ;
;     Combinational ALUTs       ; 144                                           ;
;     Memory ALUTs              ; 0                                             ;
;     Dedicated logic registers ; 0                                             ;
; Total registers               ; 0                                             ;
; Total pins                    ; 71                                            ;
; Total virtual pins            ; 0                                             ;
; Total block memory bits       ; 0                                             ;
; DSP block 18-bit elements     ; 0                                             ;
; Total PLLs                    ; 0                                             ;
; Total DLLs                    ; 0                                             ;
+-------------------------------+-----------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings                                                                                        ;
+----------------------------------------------------------------------------+--------------------+--------------------+
; Option                                                                     ; Setting            ; Default Value      ;
+----------------------------------------------------------------------------+--------------------+--------------------+
; Device                                                                     ; EP3SE50F484C2      ;                    ;
; Top-level entity name                                                      ; agc                ; agc                ;
; Family name                                                                ; Stratix III        ; Stratix II         ;
; Use smart compilation                                                      ; Off                ; Off                ;
; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On                 ; On                 ;
; Enable compact report table                                                ; Off                ; Off                ;
; Restructure Multiplexers                                                   ; Auto               ; Auto               ;
; Create Debugging Nodes for IP Cores                                        ; Off                ; Off                ;
; Preserve fewer node names                                                  ; On                 ; On                 ;
; Disable OpenCore Plus hardware evaluation                                  ; Off                ; Off                ;
; Verilog Version                                                            ; Verilog_2001       ; Verilog_2001       ;
; VHDL Version                                                               ; VHDL_1993          ; VHDL_1993          ;
; State Machine Processing                                                   ; Auto               ; Auto               ;
; Safe State Machine                                                         ; Off                ; Off                ;
; Extract Verilog State Machines                                             ; On                 ; On                 ;
; Extract VHDL State Machines                                                ; On                 ; On                 ;
; Ignore Verilog initial constructs                                          ; Off                ; Off                ;
; Iteration limit for constant Verilog loops                                 ; 5000               ; 5000               ;
; Iteration limit for non-constant Verilog loops                             ; 250                ; 250                ;