agc.fit.rpt

AGC verilog实现

; Optimize Hold Timing                                                       ; All Paths                                               ; All Paths                                               ;
; Optimize Multi-Corner Timing                                               ; Off                                                     ; Off                                                     ;
; Auto RAM to MLAB Conversion                                                ; On                                                      ; On                                                      ;
; Equivalent RAM and MLAB Power Up                                           ; Auto                                                    ; Auto                                                    ;
; Equivalent RAM and MLAB Paused Read Capabilities                           ; Care                                                    ; Care                                                    ;
; Programmable Power Technology Optimization                                 ; Force All Tiles with Failing Timing Paths to High Speed ; Force All Tiles with Failing Timing Paths to High Speed ;
; Programmable Power Maximum High-Speed Fraction of Used LAB Tiles           ; 1.0                                                     ; 1.0                                                     ;
; PowerPlay Power Optimization                                               ; Normal compilation                                      ; Normal compilation                                      ;
; SSN Optimization                                                           ; Off                                                     ; Off                                                     ;
; Optimize Timing                                                            ; Normal compilation                                      ; Normal compilation                                      ;
; Optimize Timing for ECOs                                                   ; Off                                                     ; Off                                                     ;
; Regenerate full fit report during ECO compiles                             ; Off                                                     ; Off                                                     ;
; Optimize IOC Register Placement for Timing                                 ; Normal                                                  ; Normal                                                  ;
; Limit to One Fitting Attempt                                               ; Off                                                     ; Off                                                     ;
; Final Placement Optimizations                                              ; Automatically                                           ; Automatically                                           ;
; Fitter Aggressive Routability Optimizations                                ; Automatically                                           ; Automatically                                           ;
; Fitter Initial Placement Seed                                              ; 1                                                       ; 1                                                       ;
; Weak Pull-Up Resistor                                                      ; Off                                                     ; Off                                                     ;
; Enable Bus-Hold Circuitry                                                  ; Off                                                     ; Off                                                     ;
; Auto Packed Registers                                                      ; Auto                                                    ; Auto                                                    ;
; Auto Delay Chains                                                          ; On                                                      ; On                                                      ;
; Allow Single-ended Buffer for Differential-XSTL Input                      ; Off                                                     ; Off                                                     ;
; Treat Bidirectional Pin as Output Pin                                      ; Off                                                     ; Off                                                     ;
; Auto Merge PLLs                                                            ; On                                                      ; On                                                      ;
; Perform Physical Synthesis for Combinational Logic for Fitting             ; Off                                                     ; Off                                                     ;
; Perform Physical Synthesis for Combinational Logic for Performance         ; Off                                                     ; Off                                                     ;
; Perform Register Duplication for Performance                               ; Off                                                     ; Off                                                     ;
; Perform Logic to Memory Mapping for Fitting                                ; Off                                                     ; Off                                                     ;
; Perform Register Retiming for Performance                                  ; Off                                                     ; Off                                                     ;
; Perform Asynchronous Signal Pipelining                                     ; Off                                                     ; Off                                                     ;
; Fitter Effort                                                              ; Auto Fit                                                ; Auto Fit                                                ;
; Physical Synthesis Effort Level                                            ; Normal                                                  ; Normal                                                  ;
; Logic Cell Insertion - Logic Duplication                                   ; Auto                                                    ; Auto                                                    ;
; Auto Register Duplication                                                  ; Auto                                                    ; Auto                                                    ;
; Auto Global Clock                                                          ; On                                                      ; On                                                      ;
; Auto Global Register Control Signals                                       ; On                                                      ; On                                                      ;
; Reserve all unused pins                                                    ; As input tri-stated with weak pull-up                   ; As input tri-stated with weak pull-up                   ;
; Stop After Congestion Map Generation                                       ; Off                                                     ; Off                                                     ;
; Synchronizer Identification                                                ; Off                                                     ; Off                                                     ;
; Enable Beneficial Skew Optimization                                        ; On                                                      ; On                                                      ;
; Optimize Design for Metastability                                          ; On                                                      ; On                                                      ;
; RAM Block Read Clock Duty Cycle Dependency                                 ; On                                                      ; On                                                      ;
; Maintain Compatibility with All Stratix III MRAM Versions                  ; On                                                      ; On                                                      ;
; Force Fitter to Avoid Periphery Placement Warnings                         ; Off                                                     ; Off                                                     ;
; Clamping Diode                                                             ; Off                                                     ; Off                                                     ;
; Enable input tri-state on active configuration pins in user mode           ; Off                                                     ; Off                                                     ;
+----------------------------------------------------------------------------+---------------------------------------------------------+---------------------------------------------------------+


Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time.
+-------------------------------------+
; Parallel Compilation                ;
+----------------------------+--------+
; Processors                 ; Number ;
+----------------------------+--------+
; Number detected on machine ; 2      ;
; Maximum allowed            ; 1      ;
+----------------------------+--------+


+-------------------------------------------+
; I/O Assignment Warnings                   ;
+-----------+-------------------------------+
; Pin Name  ; Reason                        ;
+-----------+-------------------------------+
; clk       ; Incomplete set of assignments ;
; power[0]  ; Incomplete set of assignments ;
; power[1]  ; Incomplete set of assignments ;
; power[2]  ; Incomplete set of assignments ;
; power[3]  ; Incomplete set of assignments ;
; power[4]  ; Incomplete set of assignments ;
; power[5]  ; Incomplete set of assignments ;
; power[6]  ; Incomplete set of assignments ;
; power[7]  ; Incomplete set of assignments ;
; power[8]  ; Incomplete set of assignments ;
; power[9]  ; Incomplete set of assignments ;
; power[10] ; Incomplete set of assignments ;
; power[11] ; Incomplete set of assignments ;
; power[12] ; Incomplete set of assignments ;
; power[13] ; Incomplete set of assignments ;
; power[14] ; Incomplete set of assignments ;
; power[15] ; Incomplete set of assignments ;
; power[16] ; Incomplete set of assignments ;
; power[17] ; Incomplete set of assignments ;
; power[18] ; Incomplete set of assignments ;
; power[19] ; Incomplete set of assignments ;
; power[20] ; Incomplete set of assignments ;
; power[21] ; Incomplete set of assignments ;
; power[22] ; Incomplete set of assignments ;
; power[23] ; Incomplete set of assignments ;
; power[24] ; Incomplete set of assignments ;
; power[25] ; Incomplete set of assignments ;
; power[26] ; Incomplete set of assignments ;
; power[27] ; Incomplete set of assignments ;
; power[28] ; Incomplete set of assignments ;
; power[29] ; Incomplete set of assignments ;
; power[30] ; Incomplete set of assignments ;
; power[31] ; Incomplete set of assignments ;
; power[32] ; Incomplete set of assignments ;
; power[33] ; Incomplete set of assignments ;
; power[34] ; Incomplete set of assignments ;
; power[35] ; Incomplete set of assignments ;
; power[36] ; Incomplete set of assignments ;
; y_out[0]  ; Incomplete set of assignments ;
; y_out[1]  ; Incomplete set of assignments ;
; y_out[2]  ; Incomplete set of assignments ;
; y_out[3]  ; Incomplete set of assignments ;