agc.map.summary

来自「AGC verilog实现」· SUMMARY 代码 · 共 17 行

Analysis & Synthesis Status : Successful - Thu Dec 01 22:18:31 2011
Quartus II Version : 10.0 Build 262 08/18/2010 SP 1 SJ Web Edition
Revision Name : agc
Top-level Entity Name : agc
Family : Stratix III
Logic utilization : N/A
    Combinational ALUTs : 144
    Memory ALUTs : 0
    Dedicated logic registers : 0
Total registers : 0
Total pins : 71
Total virtual pins : 0
Total block memory bits : 0
DSP block 18-bit elements : 0
Total PLLs : 0
Total DLLs : 0