agc.map.qmsg

AGC verilog实现

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 10.0 Build 262 08/18/2010 Service Pack 1 SJ Web Edition " "Info: Version 10.0 Build 262 08/18/2010 Service Pack 1 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Thu Dec 01 22:18:23 2011 " "Info: Processing started: Thu Dec 01 22:18:23 2011" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off agc -c agc " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off agc -c agc" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "agc.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file agc.v" { { "Info" "ISGN_ENTITY_NAME" "1 agc " "Info: Found entity 1: agc" {  } { { "agc.v" "" { Text "E:/altera/wiretx/agc/agc.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "mymult.v 2 2 " "Info: Found 2 design units, including 2 entities, in source file mymult.v" { { "Info" "ISGN_ENTITY_NAME" "1 mymult_altfp_mult_3tn " "Info: Found entity 1: mymult_altfp_mult_3tn" {  } { { "mymult.v" "" { Text "E:/altera/wiretx/agc/mymult.v" 46 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "2 mymult " "Info: Found entity 2: mymult" {  } { { "mymult.v" "" { Text "E:/altera/wiretx/agc/mymult.v" 804 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_TOP" "agc " "Info: Elaborating entity \"agc\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0 -1}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "rst agc.v(13) " "Warning (10235): Verilog HDL Always Construct warning at agc.v(13): variable \"rst\" is read inside the Always Construct but isn't in the Always Construct's Event Control" {  } { { "agc.v" "" { Text "E:/altera/wiretx/agc/agc.v" 13 0 0 } }  } 0 10235 "Verilog HDL Always Construct warning at %2!s!: variable \"%1!s!\" is read inside the Always Construct but isn't in the Always Construct's Event Control" 0 0 "" 0 -1}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "cnt agc.v(19) " "Warning (10235): Verilog HDL Always Construct warning at agc.v(19): variable \"cnt\" is read inside the Always Construct but isn't in the Always Construct's Event Control" {  } { { "agc.v" "" { Text "E:/altera/wiretx/agc/agc.v" 19 0 0 } }  } 0 10235 "Verilog HDL Always Construct warning at %2!s!: variable \"%1!s!\" is read inside the Always Construct but isn't in the Always Construct's Event Control" 0 0 "" 0 -1}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 6 agc.v(19) " "Warning (10230): Verilog HDL assignment warning at agc.v(19): truncated value with size 32 to match size of target (6)" {  } { { "agc.v" "" { Text "E:/altera/wiretx/agc/agc.v" 19 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0 -1}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "cnt agc.v(20) " "Warning (10235): Verilog HDL Always Construct warning at agc.v(20): variable \"cnt\" is read inside the Always Construct but isn't in the Always Construct's Event Control" {  } { { "agc.v" "" { Text "E:/altera/wiretx/agc/agc.v" 20 0 0 } }  } 0 10235 "Verilog HDL Always Construct warning at %2!s!: variable \"%1!s!\" is read inside the Always Construct but isn't in the Always Construct's Event Control" 0 0 "" 0 -1}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "x_power1 agc.v(21) " "Warning (10235): Verilog HDL Always Construct warning at agc.v(21): variable \"x_power1\" is read inside the Always Construct but isn't in the Always Construct's Event Control" {  } { { "agc.v" "" { Text "E:/altera/wiretx/agc/agc.v" 21 0 0 } }  } 0 10235 "Verilog HDL Always Construct warning at %2!s!: variable \"%1!s!\" is read inside the Always Construct but isn't in the Always Construct's Event Control" 0 0 "" 0 -1}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "x_out agc.v(22) " "Warning (10235): Verilog HDL Always Construct warning at agc.v(22): variable \"x_out\" is read inside the Always Construct but isn't in the Always Construct's Event Control" {  } { { "agc.v" "" { Text "E:/altera/wiretx/agc/agc.v" 22 0 0 } }  } 0 10235 "Verilog HDL Always Construct warning at %2!s!: variable \"%1!s!\" is read inside the Always Construct but isn't in the Always Construct's Event Control" 0 0 "" 0 -1}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "x_power1 agc.v(26) " "Warning (10235): Verilog HDL Always Construct warning at agc.v(26): variable \"x_power1\" is read inside the Always Construct but isn't in the Always Construct's Event Control" {  } { { "agc.v" "" { Text "E:/altera/wiretx/agc/agc.v" 26 0 0 } }  } 0 10235 "Verilog HDL Always Construct warning at %2!s!: variable \"%1!s!\" is read inside the Always Construct but isn't in the Always Construct's Event Control" 0 0 "" 0 -1}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "x_out agc.v(26) " "Warning (10235): Verilog HDL Always Construct warning at agc.v(26): variable \"x_out\" is read inside the Always Construct but isn't in the Always Construct's Event Control" {  } { { "agc.v" "" { Text "E:/altera/wiretx/agc/agc.v" 26 0 0 } }  } 0 10235 "Verilog HDL Always Construct warning at %2!s!: variable \"%1!s!\" is read inside the Always Construct but isn't in the Always Construct's Event Control" 0 0 "" 0 -1}
{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "x_power agc.v(12) " "Warning (10240): Verilog HDL Always Construct warning at agc.v(12): inferring latch(es) for variable \"x_power\", which holds its previous value in one or more paths through the always construct" {  } { { "agc.v" "" { Text "E:/altera/wiretx/agc/agc.v" 12 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "" 0 -1}
{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "x_power1 agc.v(12) " "Warning (10240): Verilog HDL Always Construct warning at agc.v(12): inferring latch(es) for variable \"x_power1\", which holds its previous value in one or more paths through the always construct" {  } { { "agc.v" "" { Text "E:/altera/wiretx/agc/agc.v" 12 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "" 0 -1}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "x_power1\[0\] agc.v(12) " "Info (10041): Inferred latch for \"x_power1\[0\]\" at agc.v(12)" {  } { { "agc.v" "" { Text "E:/altera/wiretx/agc/agc.v" 12 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "x_power1\[1\] agc.v(12) " "Info (10041): Inferred latch for \"x_power1\[1\]\" at agc.v(12)" {  } { { "agc.v" "" { Text "E:/altera/wiretx/agc/agc.v" 12 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "x_power1\[2\] agc.v(12) " "Info (10041): Inferred latch for \"x_power1\[2\]\" at agc.v(12)" {  } { { "agc.v" "" { Text "E:/altera/wiretx/agc/agc.v" 12 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "x_power1\[3\] agc.v(12) " "Info (10041): Inferred latch for \"x_power1\[3\]\" at agc.v(12)" {  } { { "agc.v" "" { Text "E:/altera/wiretx/agc/agc.v" 12 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "x_power1\[4\] agc.v(12) " "Info (10041): Inferred latch for \"x_power1\[4\]\" at agc.v(12)" {  } { { "agc.v" "" { Text "E:/altera/wiretx/agc/agc.v" 12 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "x_power1\[5\] agc.v(12) " "Info (10041): Inferred latch for \"x_power1\[5\]\" at agc.v(12)" {  } { { "agc.v" "" { Text "E:/altera/wiretx/agc/agc.v" 12 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "x_power1\[6\] agc.v(12) " "Info (10041): Inferred latch for \"x_power1\[6\]\" at agc.v(12)" {  } { { "agc.v" "" { Text "E:/altera/wiretx/agc/agc.v" 12 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "x_power1\[7\] agc.v(12) " "Info (10041): Inferred latch for \"x_power1\[7\]\" at agc.v(12)" {  } { { "agc.v" "" { Text "E:/altera/wiretx/agc/agc.v" 12 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "x_power1\[8\] agc.v(12) " "Info (10041): Inferred latch for \"x_power1\[8\]\" at agc.v(12)" {  } { { "agc.v" "" { Text "E:/altera/wiretx/agc/agc.v" 12 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 -1}