add_sub_68c.tdf

AGC verilog实现

--lpm_add_sub CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 DEVICE_FAMILY="Stratix III" LPM_PIPELINE=0 LPM_WIDTH=10 cin dataa datab result
--VERSION_BEGIN 10.0SP1 cbx_cycloneii 2010:08:18:22:25:40:SJ cbx_lpm_add_sub 2010:08:18:22:25:40:SJ cbx_mgl 2010:08:18:22:28:55:SJ cbx_stratix 2010:08:18:22:25:41:SJ cbx_stratixii 2010:08:18:22:25:41:SJ  VERSION_END


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--synthesis_resources = lut 10 
SUBDESIGN add_sub_68c
( 
	cin	:	input;
	dataa[9..0]	:	input;
	datab[9..0]	:	input;
	result[9..0]	:	output;
) 
VARIABLE
	result_int[10..0]	:	WIRE;
BEGIN 
	result_int[] = (dataa[], cin) + (datab[], cin);
	result[] = result_int[10..1];
END;
--VALID FILE