mult_1ks.tdf

AGC verilog实现

--lpm_mult CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEDICATED_MULTIPLIER_CIRCUITRY="YES" DEVICE_FAMILY="Stratix III" DSP_BLOCK_BALANCING="Auto" LPM_PIPELINE=5 LPM_REPRESENTATION="UNSIGNED" LPM_WIDTHA=24 LPM_WIDTHB=24 LPM_WIDTHP=48 LPM_WIDTHS=1 clock dataa datab result CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48
--VERSION_BEGIN 10.0SP1 cbx_cycloneii 2010:08:18:22:25:40:SJ cbx_lpm_add_sub 2010:08:18:22:25:40:SJ cbx_lpm_mult 2010:08:18:22:25:40:SJ cbx_mgl 2010:08:18:22:28:55:SJ cbx_padd 2010:08:18:22:25:40:SJ cbx_stratix 2010:08:18:22:25:41:SJ cbx_stratixii 2010:08:18:22:25:41:SJ cbx_util_mgl 2010:08:18:22:25:41:SJ  VERSION_END


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FUNCTION stratixiii_mac_mult (aclr[3..0], clk[3..0], dataa[dataa_width-1..0], datab[datab_width-1..0], ena[3..0], signa, signb)
WITH ( dataa_clear, dataa_clock, dataa_width, datab_clear, datab_clock, datab_width, scanouta_clear, scanouta_clock, signa_clear, signa_clock, signa_internally_grounded, signb_clear, signb_clock, signb_internally_grounded)
RETURNS ( dataout[dataa_width+datab_width-1..0], scanouta[dataa_width-1..0]);
FUNCTION stratixiii_mac_out (aclr[3..0], chainin[chainin_width-1..0], clk[3..0], dataa[dataa_width-1..0], datab[datab_width-1..0], datac[datac_width-1..0], datad[datad_width-1..0], ena[3..0], rotate, round, roundchainout, saturate, saturatechainout, shiftright, signa, signb, zeroacc, zerochainout, zeroloopback)
WITH ( acc_adder_operation, chainin_width = 1, dataa_width = 1, datab_width = 1, datac_width = 1, datad_width = 1, dataout_width = 72, first_adder0_clear, first_adder0_clock, first_adder0_mode, first_adder1_clear, first_adder1_clock, first_adder1_mode, multa_signa_internally_grounded, multa_signb_internally_grounded, multb_signa_internally_grounded, multb_signb_internally_grounded, multc_signa_internally_grounded, multc_signb_internally_grounded, multd_signa_internally_grounded, multd_signb_internally_grounded, operation_mode, output_clear, output_clock, rotate_clear, rotate_clock, rotate_output_clear, rotate_output_clock, rotate_pipeline_clear, rotate_pipeline_clock, round_chain_out_mode, round_chain_out_width, round_clear, round_clock, round_mode, round_pipeline_clear, round_pipeline_clock, round_width, roundchainout_clear, roundchainout_clock, roundchainout_output_clear, roundchainout_output_clock, roundchainout_pipeline_clear, roundchainout_pipeline_clock, saturate_chain_out_mode, saturate_chain_out_width, saturate_clear, saturate_clock, saturate_mode, saturate_pipeline_clear, saturate_pipeline_clock, saturate_width, saturatechainout_clear, saturatechainout_clock, saturatechainout_output_clear, saturatechainout_output_clock, saturatechainout_pipeline_clear, saturatechainout_pipeline_clock, second_adder_clear, second_adder_clock, shiftright_clear, shiftright_clock, shiftright_output_clear, shiftright_output_clock, shiftright_pipeline_clear, shiftright_pipeline_clock, signa_clear, signa_clock, signa_pipeline_clear, signa_pipeline_clock, signb_clear, signb_clock, signb_pipeline_clear, signb_pipeline_clock, zeroacc_clear, zeroacc_clock, zeroacc_pipeline_clear, zeroacc_pipeline_clock, zerochainout_output_clear, zerochainout_output_clock, zeroloopback_clear, zeroloopback_clock, zeroloopback_output_clear, zeroloopback_output_clock, zeroloopback_pipeline_clear, zeroloopback_pipeline_clock)
RETURNS ( dataout[dataout_width-1..0], dftout, loopbackout[17..0], overflow, saturatechainoutoverflow);

--synthesis_resources = dsp_18bit 4 reg 96 
SUBDESIGN mult_1ks
( 
	clock	:	input;
	dataa[23..0]	:	input;
	datab[23..0]	:	input;
	result[47..0]	:	output;
) 
VARIABLE 
	dffe6a[47..0] : dffe;
	dffe7a[47..0] : dffe;
	mac_mult1 : stratixiii_mac_mult
		WITH (
			dataa_clear = "0",
			dataa_clock = "0",
			dataa_width = 18,
			datab_clear = "0",
			datab_clock = "0",
			datab_width = 18,
			signa_internally_grounded = "true",
			signb_internally_grounded = "true"
		);
	mac_mult2 : stratixiii_mac_mult
		WITH (
			dataa_clear = "0",
			dataa_clock = "0",
			dataa_width = 18,
			datab_clear = "0",
			datab_clock = "0",
			datab_width = 18
		);
	mac_mult3 : stratixiii_mac_mult
		WITH (
			dataa_clear = "0",
			dataa_clock = "0",
			dataa_width = 18,
			datab_clear = "0",
			datab_clock = "0",
			datab_width = 18,
			signb_internally_grounded = "true"
		);
	mac_mult4 : stratixiii_mac_mult
		WITH (
			dataa_clear = "0",
			dataa_clock = "0",
			dataa_width = 18,
			datab_clear = "0",
			datab_clock = "0",
			datab_width = 18,
			signa_internally_grounded = "true"
		);
	mac_out5 : stratixiii_mac_out
		WITH (
			dataa_width = 36,
			datab_width = 36,
			datac_width = 36,
			datad_width = 36,
			dataout_width = 72,
			first_adder0_clear = "0",
			first_adder0_clock = "0",
			first_adder1_clear = "0",
			first_adder1_clock = "0",
			operation_mode = "36_bit_multiply",
			output_clear = "0",
			output_clock = "0"
		);
	aclr	: NODE;
	clken	: NODE;

BEGIN 
	dffe6a[].clk = clock;
	dffe6a[].clrn = (! aclr);
	dffe6a[].d = mac_out5.dataout[71..24];
	dffe6a[].ena = clken;
	dffe7a[].clk = clock;
	dffe7a[].clrn = (! aclr);
	dffe7a[].d = dffe6a[].q;
	dffe7a[].ena = clken;
	mac_mult1.aclr[] = aclr;
	mac_mult1.clk[] = clock;
	mac_mult1.dataa[] = ( dataa[5..0], B"000000000000");
	mac_mult1.datab[] = ( datab[5..0], B"000000000000");
	mac_mult1.ena[] = clken;
	mac_mult1.signa = B"0";
	mac_mult1.signb = B"0";
	mac_mult2.aclr[] = aclr;
	mac_mult2.clk[] = clock;
	mac_mult2.dataa[17..0] = dataa[23..6];
	mac_mult2.datab[17..0] = datab[23..6];
	mac_mult2.ena[] = clken;
	mac_mult2.signa = B"0";
	mac_mult2.signb = B"0";
	mac_mult3.aclr[] = aclr;
	mac_mult3.clk[] = clock;
	mac_mult3.dataa[17..0] = dataa[23..6];
	mac_mult3.datab[] = ( datab[5..0], B"000000000000");
	mac_mult3.ena[] = clken;
	mac_mult3.signa = B"0";
	mac_mult3.signb = B"0";
	mac_mult4.aclr[] = aclr;
	mac_mult4.clk[] = clock;
	mac_mult4.dataa[] = ( dataa[5..0], B"000000000000");
	mac_mult4.datab[17..0] = datab[23..6];
	mac_mult4.ena[] = clken;
	mac_mult4.signa = B"0";
	mac_mult4.signb = B"0";
	mac_out5.aclr[] = aclr;
	mac_out5.clk[] = clock;
	mac_out5.dataa[] = mac_mult2.dataout[];
	mac_out5.datab[] = mac_mult4.dataout[];
	mac_out5.datac[] = mac_mult3.dataout[];
	mac_out5.datad[] = mac_mult1.dataout[];
	mac_out5.ena[] = clken;
	mac_out5.signa = B"0";
	mac_out5.signb = B"0";
	aclr = GND;
	clken = VCC;
	result[] = dffe7a[].q;
END;
--VALID FILE