prev_cmp_agc.qmsg

AGC verilog实现

{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "x_power1\[9\] agc.v(12) " "Info (10041): Inferred latch for \"x_power1\[9\]\" at agc.v(12)" {  } { { "agc.v" "" { Text "E:/altera/wiretx/agc/agc.v" 12 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "x_power1\[10\] agc.v(12) " "Info (10041): Inferred latch for \"x_power1\[10\]\" at agc.v(12)" {  } { { "agc.v" "" { Text "E:/altera/wiretx/agc/agc.v" 12 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "x_power1\[11\] agc.v(12) " "Info (10041): Inferred latch for \"x_power1\[11\]\" at agc.v(12)" {  } { { "agc.v" "" { Text "E:/altera/wiretx/agc/agc.v" 12 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "x_power1\[12\] agc.v(12) " "Info (10041): Inferred latch for \"x_power1\[12\]\" at agc.v(12)" {  } { { "agc.v" "" { Text "E:/altera/wiretx/agc/agc.v" 12 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "x_power1\[13\] agc.v(12) " "Info (10041): Inferred latch for \"x_power1\[13\]\" at agc.v(12)" {  } { { "agc.v" "" { Text "E:/altera/wiretx/agc/agc.v" 12 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "x_power1\[14\] agc.v(12) " "Info (10041): Inferred latch for \"x_power1\[14\]\" at agc.v(12)" {  } { { "agc.v" "" { Text "E:/altera/wiretx/agc/agc.v" 12 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "x_power1\[15\] agc.v(12) " "Info (10041): Inferred latch for \"x_power1\[15\]\" at agc.v(12)" {  } { { "agc.v" "" { Text "E:/altera/wiretx/agc/agc.v" 12 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "x_power1\[16\] agc.v(12) " "Info (10041): Inferred latch for \"x_power1\[16\]\" at agc.v(12)" {  } { { "agc.v" "" { Text "E:/altera/wiretx/agc/agc.v" 12 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "x_power1\[17\] agc.v(12) " "Info (10041): Inferred latch for \"x_power1\[17\]\" at agc.v(12)" {  } { { "agc.v" "" { Text "E:/altera/wiretx/agc/agc.v" 12 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "x_power1\[18\] agc.v(12) " "Info (10041): Inferred latch for \"x_power1\[18\]\" at agc.v(12)" {  } { { "agc.v" "" { Text "E:/altera/wiretx/agc/agc.v" 12 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "x_power1\[19\] agc.v(12) " "Info (10041): Inferred latch for \"x_power1\[19\]\" at agc.v(12)" {  } { { "agc.v" "" { Text "E:/altera/wiretx/agc/agc.v" 12 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "x_power1\[20\] agc.v(12) " "Info (10041): Inferred latch for \"x_power1\[20\]\" at agc.v(12)" {  } { { "agc.v" "" { Text "E:/altera/wiretx/agc/agc.v" 12 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "x_power1\[21\] agc.v(12) " "Info (10041): Inferred latch for \"x_power1\[21\]\" at agc.v(12)" {  } { { "agc.v" "" { Text "E:/altera/wiretx/agc/agc.v" 12 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "x_power1\[22\] agc.v(12) " "Info (10041): Inferred latch for \"x_power1\[22\]\" at agc.v(12)" {  } { { "agc.v" "" { Text "E:/altera/wiretx/agc/agc.v" 12 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "x_power1\[23\] agc.v(12) " "Info (10041): Inferred latch for \"x_power1\[23\]\" at agc.v(12)" {  } { { "agc.v" "" { Text "E:/altera/wiretx/agc/agc.v" 12 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "x_power1\[24\] agc.v(12) " "Info (10041): Inferred latch for \"x_power1\[24\]\" at agc.v(12)" {  } { { "agc.v" "" { Text "E:/altera/wiretx/agc/agc.v" 12 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "x_power1\[25\] agc.v(12) " "Info (10041): Inferred latch for \"x_power1\[25\]\" at agc.v(12)" {  } { { "agc.v" "" { Text "E:/altera/wiretx/agc/agc.v" 12 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "x_power1\[26\] agc.v(12) " "Info (10041): Inferred latch for \"x_power1\[26\]\" at agc.v(12)" {  } { { "agc.v" "" { Text "E:/altera/wiretx/agc/agc.v" 12 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "x_power1\[27\] agc.v(12) " "Info (10041): Inferred latch for \"x_power1\[27\]\" at agc.v(12)" {  } { { "agc.v" "" { Text "E:/altera/wiretx/agc/agc.v" 12 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "x_power1\[28\] agc.v(12) " "Info (10041): Inferred latch for \"x_power1\[28\]\" at agc.v(12)" {  } { { "agc.v" "" { Text "E:/altera/wiretx/agc/agc.v" 12 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "x_power1\[29\] agc.v(12) " "Info (10041): Inferred latch for \"x_power1\[29\]\" at agc.v(12)" {  } { { "agc.v" "" { Text "E:/altera/wiretx/agc/agc.v" 12 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "x_power1\[30\] agc.v(12) " "Info (10041): Inferred latch for \"x_power1\[30\]\" at agc.v(12)" {  } { { "agc.v" "" { Text "E:/altera/wiretx/agc/agc.v" 12 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "x_power1\[31\] agc.v(12) " "Info (10041): Inferred latch for \"x_power1\[31\]\" at agc.v(12)" {  } { { "agc.v" "" { Text "E:/altera/wiretx/agc/agc.v" 12 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "x_power1\[32\] agc.v(12) " "Info (10041): Inferred latch for \"x_power1\[32\]\" at agc.v(12)" {  } { { "agc.v" "" { Text "E:/altera/wiretx/agc/agc.v" 12 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "x_power1\[33\] agc.v(12) " "Info (10041): Inferred latch for \"x_power1\[33\]\" at agc.v(12)" {  } { { "agc.v" "" { Text "E:/altera/wiretx/agc/agc.v" 12 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 -1}