agc.eda.qmsg

AGC verilog实现

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus II " "Info: Running Quartus II EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 10.0 Build 262 08/18/2010 Service Pack 1 SJ Web Edition " "Info: Version 10.0 Build 262 08/18/2010 Service Pack 1 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Thu Dec 01 22:19:25 2011 " "Info: Processing started: Thu Dec 01 22:19:25 2011" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --read_settings_files=off --write_settings_files=off agc -c agc " "Info: Command: quartus_eda --read_settings_files=off --write_settings_files=off agc -c agc" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
{ "Info" "IWSC_GENERATED_NON_HIERARCHICAL_SIMULATION_NETLIST" "" "Info: Generated simulation netlist will be non-hierarchical because the design has SignalTap II partitions, termination control logic and/or a design partition that contains bidirectional ports" {  } {  } 0 0 "Generated simulation netlist will be non-hierarchical because the design has SignalTap II partitions, termination control logic and/or a design partition that contains bidirectional ports" 0 0 "" 0 -1}
{ "Info" "IWSC_DONE_HDL_GENERATION" "agc_2_1100mv_85c_slow.vo E:/altera/wiretx/agc/simulation/modelsim/ simulation " "Info: Generated file agc_2_1100mv_85c_slow.vo in folder \"E:/altera/wiretx/agc/simulation/modelsim/\" for EDA simulation tool" {  } {  } 0 0 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "" 0 -1}
{ "Info" "IWSC_DONE_HDL_GENERATION" "agc_2_1100mv_0c_slow.vo E:/altera/wiretx/agc/simulation/modelsim/ simulation " "Info: Generated file agc_2_1100mv_0c_slow.vo in folder \"E:/altera/wiretx/agc/simulation/modelsim/\" for EDA simulation tool" {  } {  } 0 0 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "" 0 -1}
{ "Info" "IWSC_DONE_HDL_GENERATION" "agc_min_1100mv_0c_fast.vo E:/altera/wiretx/agc/simulation/modelsim/ simulation " "Info: Generated file agc_min_1100mv_0c_fast.vo in folder \"E:/altera/wiretx/agc/simulation/modelsim/\" for EDA simulation tool" {  } {  } 0 0 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "" 0 -1}
{ "Info" "IWSC_DONE_HDL_GENERATION" "agc.vo E:/altera/wiretx/agc/simulation/modelsim/ simulation " "Info: Generated file agc.vo in folder \"E:/altera/wiretx/agc/simulation/modelsim/\" for EDA simulation tool" {  } {  } 0 0 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "" 0 -1}
{ "Info" "IWSC_DONE_HDL_GENERATION" "agc_2_1100mv_85c_v_slow.sdo E:/altera/wiretx/agc/simulation/modelsim/ simulation " "Info: Generated file agc_2_1100mv_85c_v_slow.sdo in folder \"E:/altera/wiretx/agc/simulation/modelsim/\" for EDA simulation tool" {  } {  } 0 0 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "" 0 -1}
{ "Info" "IWSC_DONE_HDL_GENERATION" "agc_2_1100mv_0c_v_slow.sdo E:/altera/wiretx/agc/simulation/modelsim/ simulation " "Info: Generated file agc_2_1100mv_0c_v_slow.sdo in folder \"E:/altera/wiretx/agc/simulation/modelsim/\" for EDA simulation tool" {  } {  } 0 0 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "" 0 -1}
{ "Info" "IWSC_DONE_HDL_GENERATION" "agc_min_1100mv_0c_v_fast.sdo E:/altera/wiretx/agc/simulation/modelsim/ simulation " "Info: Generated file agc_min_1100mv_0c_v_fast.sdo in folder \"E:/altera/wiretx/agc/simulation/modelsim/\" for EDA simulation tool" {  } {  } 0 0 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "" 0 -1}
{ "Info" "IWSC_DONE_HDL_GENERATION" "agc_v.sdo E:/altera/wiretx/agc/simulation/modelsim/ simulation " "Info: Generated file agc_v.sdo in folder \"E:/altera/wiretx/agc/simulation/modelsim/\" for EDA simulation tool" {  } {  } 0 0 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "" 0 -1}
{ "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 0 s Quartus II " "Info: Quartus II EDA Netlist Writer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "206 " "Info: Peak virtual memory: 206 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Thu Dec 01 22:19:28 2011 " "Info: Processing ended: Thu Dec 01 22:19:28 2011" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Info: Elapsed time: 00:00:03" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Info: Total CPU time (on all processors): 00:00:02" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}