add_sub_hge.tdf

AGC verilog实现

--lpm_add_sub CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 DEVICE_FAMILY="Stratix III" LPM_PIPELINE=1 LPM_WIDTH=9 aclr(gnd) cin clken(vcc) clock dataa datab result
--VERSION_BEGIN 10.0SP1 cbx_cycloneii 2010:08:18:22:25:40:SJ cbx_lpm_add_sub 2010:08:18:22:25:40:SJ cbx_mgl 2010:08:18:22:28:55:SJ cbx_stratix 2010:08:18:22:25:41:SJ cbx_stratixii 2010:08:18:22:25:41:SJ  VERSION_END


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--synthesis_resources = lut 9 
SUBDESIGN add_sub_hge
( 
	aclr	:	input;
	cin	:	input;
	clken	:	input;
	clock	:	input;
	dataa[8..0]	:	input;
	datab[8..0]	:	input;
	result[8..0]	:	output;
) 
VARIABLE
	pipeline_dffe[8..0]	:	DFFE
		WITH (
			power_up ="low"
		);
	result_int[9..0]	:	WIRE;
	const_used_aclr	:	WIRE;
	const_used_clken	:	WIRE;
BEGIN 
	result_int[] = (dataa[], cin) + (datab[], cin);
	pipeline_dffe[].clk = clock;
	result[] = pipeline_dffe[8..0].q;
	pipeline_dffe[8..0].d = result_int[9..1];
	const_used_aclr = aclr;
	const_used_clken = clken;
END;
--VALID FILE