agc.fit.qmsg

AGC verilog实现

{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP3SL50F484C2 " "Info: Device EP3SL50F484C2 is compatible" {  } {  } 2 0 "Device %1!s! is compatible" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP3SL70F484C2 " "Info: Device EP3SL70F484C2 is compatible" {  } {  } 2 0 "Device %1!s! is compatible" 0 0 "" 0 -1}  } {  } 2 0 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "" 0 -1}
{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "1 " "Info: Fitter converted 1 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DATA0~ J18 " "Info: Pin ~ALTERA_DATA0~ is reserved at location J18" {  } { { "e:/altera/10.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "e:/altera/10.0sp1/quartus/bin/pin_planner.ppl" { ~ALTERA_DATA0~ } } } { "e:/altera/10.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/10.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~ALTERA_DATA0~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "E:/altera/wiretx/agc/" 0 { } { { 0 { 0 ""} 0 333 4858 5830 0}  }  } }  } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "" 0 -1}
{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Warning: Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" {  } {  } 0 0 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "" 0 -1}