agc.eda.rpt

AGC verilog实现

EDA Netlist Writer report for agc
Thu Dec 01 22:19:28 2011
Quartus II Version 10.0 Build 262 08/18/2010 Service Pack 1 SJ Web Edition


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. EDA Netlist Writer Summary
  3. Simulation Settings
  4. Simulation Generated Files
  5. EDA Netlist Writer Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2010 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+-------------------------------------------------------------------+
; EDA Netlist Writer Summary                                        ;
+---------------------------+---------------------------------------+
; EDA Netlist Writer Status ; Successful - Thu Dec 01 22:19:28 2011 ;
; Revision Name             ; agc                                   ;
; Top-level Entity Name     ; agc                                   ;
; Family                    ; Stratix III                           ;
; Simulation Files Creation ; Successful                            ;
+---------------------------+---------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------+
; Simulation Settings                                                                                                           ;
+---------------------------------------------------------------------------------------------------+---------------------------+
; Option                                                                                            ; Setting                   ;
+---------------------------------------------------------------------------------------------------+---------------------------+
; Tool Name                                                                                         ; ModelSim-Altera (Verilog) ;
; Generate netlist for functional simulation only                                                   ; Off                       ;
; Time scale                                                                                        ; 1 ps                      ;
; Truncate long hierarchy paths                                                                     ; Off                       ;
; Map illegal HDL characters                                                                        ; Off                       ;
; Flatten buses into individual nodes                                                               ; Off                       ;
; Maintain hierarchy                                                                                ; Off                       ;
; Bring out device-wide set/reset signals as ports                                                  ; Off                       ;
; Enable glitch filtering                                                                           ; Off                       ;
; Do not write top level VHDL entity                                                                ; Off                       ;
; Disable detection of setup and hold time violations in the input registers of bi-directional pins ; Off                       ;
; Architecture name in VHDL output netlist                                                          ; structure                 ;
; Generate third-party EDA tool command script for RTL functional simulation                        ; Off                       ;
; Generate third-party EDA tool command script for gate-level simulation                            ; Off                       ;
+---------------------------------------------------------------------------------------------------+---------------------------+


+-----------------------------------------------------------------------+
; Simulation Generated Files                                            ;
+-----------------------------------------------------------------------+
; Generated Files                                                       ;
+-----------------------------------------------------------------------+
; E:/altera/wiretx/agc/simulation/modelsim/agc_2_1100mv_85c_slow.vo     ;
; E:/altera/wiretx/agc/simulation/modelsim/agc_2_1100mv_0c_slow.vo      ;
; E:/altera/wiretx/agc/simulation/modelsim/agc_min_1100mv_0c_fast.vo    ;
; E:/altera/wiretx/agc/simulation/modelsim/agc.vo                       ;
; E:/altera/wiretx/agc/simulation/modelsim/agc_2_1100mv_85c_v_slow.sdo  ;
; E:/altera/wiretx/agc/simulation/modelsim/agc_2_1100mv_0c_v_slow.sdo   ;
; E:/altera/wiretx/agc/simulation/modelsim/agc_min_1100mv_0c_v_fast.sdo ;
; E:/altera/wiretx/agc/simulation/modelsim/agc_v.sdo                    ;
+-----------------------------------------------------------------------+


+-----------------------------+
; EDA Netlist Writer Messages ;
+-----------------------------+
Info: *******************************************************************
Info: Running Quartus II EDA Netlist Writer
    Info: Version 10.0 Build 262 08/18/2010 Service Pack 1 SJ Web Edition
    Info: Processing started: Thu Dec 01 22:19:25 2011
Info: Command: quartus_eda --read_settings_files=off --write_settings_files=off agc -c agc
Info: Generated simulation netlist will be non-hierarchical because the design has SignalTap II partitions, termination control logic and/or a design partition that contains bidirectional ports
Info: Generated file agc_2_1100mv_85c_slow.vo in folder "E:/altera/wiretx/agc/simulation/modelsim/" for EDA simulation tool
Info: Generated file agc_2_1100mv_0c_slow.vo in folder "E:/altera/wiretx/agc/simulation/modelsim/" for EDA simulation tool
Info: Generated file agc_min_1100mv_0c_fast.vo in folder "E:/altera/wiretx/agc/simulation/modelsim/" for EDA simulation tool
Info: Generated file agc.vo in folder "E:/altera/wiretx/agc/simulation/modelsim/" for EDA simulation tool
Info: Generated file agc_2_1100mv_85c_v_slow.sdo in folder "E:/altera/wiretx/agc/simulation/modelsim/" for EDA simulation tool
Info: Generated file agc_2_1100mv_0c_v_slow.sdo in folder "E:/altera/wiretx/agc/simulation/modelsim/" for EDA simulation tool
Info: Generated file agc_min_1100mv_0c_v_fast.sdo in folder "E:/altera/wiretx/agc/simulation/modelsim/" for EDA simulation tool
Info: Generated file agc_v.sdo in folder "E:/altera/wiretx/agc/simulation/modelsim/" for EDA simulation tool
Info: Quartus II EDA Netlist Writer was successful. 0 errors, 0 warnings
    Info: Peak virtual memory: 206 megabytes
    Info: Processing ended: Thu Dec 01 22:19:28 2011
    Info: Elapsed time: 00:00:03
    Info: Total CPU time (on all processors): 00:00:02