agc.v

AGC verilog实现

module agc(clk,rst,x_in,power,y_out);
parameter MN=64250;
input clk;
input rst;
input [15:0]x_in;
output [15:0]y_out;
output [36:0]power;
reg[36:0]x_power,x_power1;
reg[5:0]cnt;
wire[31:0]x_out;

always@(clk)begin
	if(!rst)begin
		x_power<=0;
		x_power<=0;
		cnt<=0;
	end
	else begin
		cnt<=cnt+1;
		if(cnt==0)begin
			x_power<=x_power1;
			x_power1<={{5{x_out[31]}},x_out};

		end
		else
			x_power1<=x_power1+{{5{x_out[31]}},x_out};
		end
end

assign y_out=(x_power<MN)?(x_in<<1):(x_in>>1);
assign power=x_power;

mymult mymult(
				.clock(clk),
				.dataa(x_in),
				.datab(x_in),
				.result(x_out)
				);

endmodule