agc.fit.summary

来自「AGC verilog实现」· SUMMARY 代码 · 共 19 行

Fitter Status : Successful - Thu Dec 01 22:18:55 2011
Quartus II Version : 10.0 Build 262 08/18/2010 SP 1 SJ Web Edition
Revision Name : agc
Top-level Entity Name : agc
Family : Stratix III
Device : EP3SE50F484C2
Timing Models : Final
Logic utilization : < 1 %
    Combinational ALUTs : 144 / 38,000 ( < 1 % )
    Memory ALUTs : 0 / 19,000 ( 0 % )
    Dedicated logic registers : 0 / 38,000 ( 0 % )
Total registers : 0
Total pins : 71 / 296 ( 24 % )
Total virtual pins : 0
Total block memory bits : 0 / 5,455,872 ( 0 % )
DSP block 18-bit elements : 0 / 384 ( 0 % )
Total PLLs : 0 / 4 ( 0 % )
Total DLLs : 0 / 4 ( 0 % )