agc_2_1100mv_0c_v_slow.sdo

AGC verilog实现

// Copyright (C) 1991-2010 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions 
// and other software and tools, and its AMPP partner logic 
// functions, and any output files from any of the foregoing 
// (including device programming or simulation files), and any 
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// to the terms and conditions of the Altera Program License 
// Subscription Agreement, Altera MegaCore Function License 
// Agreement, or other applicable license agreement, including, 
// without limitation, that your use is for the sole purpose of 
// programming logic devices manufactured by Altera and sold by 
// Altera or its authorized distributors.  Please refer to the 
// applicable agreement for further details.


// 
// Device: Altera EP3SE50F484C2 Package FBGA484
// 

//
// This file contains Slow Corner delays for the design using part EP3SE50F484C2,
// with speed grade 2, core voltage 1.1V, and temperature 0 Celsius
//

// 
// This SDF file should be used for ModelSim-Altera (Verilog) only
// 

(DELAYFILE
  (SDFVERSION "2.1")
  (DESIGN "agc")
  (DATE "12/01/2011 22:19:28")
  (VENDOR "Altera")
  (PROGRAM "Quartus II")
  (VERSION "Version 10.0 Build 262 08/18/2010 Service Pack 1 SJ Web Edition")
  (DIVIDER .)
  (TIMESCALE 1 ps)

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        (PORT datad (432:432:432) (434:434:434))
        (IOPATH datac combout (177:177:177) (189:189:189))
        (IOPATH datad combout (169:169:169) (165:165:165))
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        (IOPATH dataa combout (304:304:304) (296:296:296))
        (IOPATH datab combout (310:310:310) (291:291:291))
        (IOPATH datac combout (174:174:174) (184:184:184))
        (IOPATH datad combout (170:170:170) (168:168:168))
        (IOPATH dataf combout (58:58:58) (60:60:60))
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        (IOPATH datac combout (174:174:174) (184:184:184))
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        (IOPATH datac combout (174:174:174) (184:184:184))
        (IOPATH datad combout (230:230:230) (239:239:239))
        (IOPATH datae combout (132:132:132) (138:138:138))
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