agc_2_1100mv_85c_slow.vo

AGC verilog实现

// Copyright (C) 1991-2010 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions 
// and other software and tools, and its AMPP partner logic 
// functions, and any output files from any of the foregoing 
// (including device programming or simulation files), and any 
// associated documentation or information are expressly subject 
// to the terms and conditions of the Altera Program License 
// Subscription Agreement, Altera MegaCore Function License 
// Agreement, or other applicable license agreement, including, 
// without limitation, that your use is for the sole purpose of 
// programming logic devices manufactured by Altera and sold by 
// Altera or its authorized distributors.  Please refer to the 
// applicable agreement for further details.

// VENDOR "Altera"
// PROGRAM "Quartus II"
// VERSION "Version 10.0 Build 262 08/18/2010 Service Pack 1 SJ Web Edition"

// DATE "12/01/2011 22:19:27"

// 
// Device: Altera EP3SE50F484C2 Package FBGA484
// 

// 
// This Verilog file should be used for ModelSim-Altera (Verilog) only
// 

`timescale 1 ps/ 1 ps

module agc (
	clk,
	rst,
	x_in,
	power,
	y_out);
input 	clk;
input 	rst;
input 	[15:0] x_in;
output 	[36:0] power;
output 	[15:0] y_out;

// Design Ports Information
// clk	=>  Location: PIN_D1,	 I/O Standard: 2.5 V,	 Current Strength: Default
// power[0]	=>  Location: PIN_N19,	 I/O Standard: 2.5 V,	 Current Strength: Default
// power[1]	=>  Location: PIN_T15,	 I/O Standard: 2.5 V,	 Current Strength: Default
// power[2]	=>  Location: PIN_N2,	 I/O Standard: 2.5 V,	 Current Strength: Default
// power[3]	=>  Location: PIN_M6,	 I/O Standard: 2.5 V,	 Current Strength: Default
// power[4]	=>  Location: PIN_T4,	 I/O Standard: 2.5 V,	 Current Strength: Default
// power[5]	=>  Location: PIN_M15,	 I/O Standard: 2.5 V,	 Current Strength: Default
// power[6]	=>  Location: PIN_K2,	 I/O Standard: 2.5 V,	 Current Strength: Default
// power[7]	=>  Location: PIN_J22,	 I/O Standard: 2.5 V,	 Current Strength: Default
// power[8]	=>  Location: PIN_P17,	 I/O Standard: 2.5 V,	 Current Strength: Default
// power[9]	=>  Location: PIN_M21,	 I/O Standard: 2.5 V,	 Current Strength: Default
// power[10]	=>  Location: PIN_G21,	 I/O Standard: 2.5 V,	 Current Strength: Default
// power[11]	=>  Location: PIN_L19,	 I/O Standard: 2.5 V,	 Current Strength: Default
// power[12]	=>  Location: PIN_AB16,	 I/O Standard: 2.5 V,	 Current Strength: Default
// power[13]	=>  Location: PIN_N21,	 I/O Standard: 2.5 V,	 Current Strength: Default
// power[14]	=>  Location: PIN_P16,	 I/O Standard: 2.5 V,	 Current Strength: Default
// power[15]	=>  Location: PIN_N17,	 I/O Standard: 2.5 V,	 Current Strength: Default
// power[16]	=>  Location: PIN_N22,	 I/O Standard: 2.5 V,	 Current Strength: Default
// power[17]	=>  Location: PIN_W12,	 I/O Standard: 2.5 V,	 Current Strength: Default
// power[18]	=>  Location: PIN_K1,	 I/O Standard: 2.5 V,	 Current Strength: Default
// power[19]	=>  Location: PIN_U2,	 I/O Standard: 2.5 V,	 Current Strength: Default
// power[20]	=>  Location: PIN_M16,	 I/O Standard: 2.5 V,	 Current Strength: Default
// power[21]	=>  Location: PIN_A17,	 I/O Standard: 2.5 V,	 Current Strength: Default
// power[22]	=>  Location: PIN_K16,	 I/O Standard: 2.5 V,	 Current Strength: Default
// power[23]	=>  Location: PIN_H1,	 I/O Standard: 2.5 V,	 Current Strength: Default
// power[24]	=>  Location: PIN_L20,	 I/O Standard: 2.5 V,	 Current Strength: Default
// power[25]	=>  Location: PIN_Y2,	 I/O Standard: 2.5 V,	 Current Strength: Default
// power[26]	=>  Location: PIN_M22,	 I/O Standard: 2.5 V,	 Current Strength: Default
// power[27]	=>  Location: PIN_M3,	 I/O Standard: 2.5 V,	 Current Strength: Default
// power[28]	=>  Location: PIN_K19,	 I/O Standard: 2.5 V,	 Current Strength: Default
// power[29]	=>  Location: PIN_C16,	 I/O Standard: 2.5 V,	 Current Strength: Default
// power[30]	=>  Location: PIN_M4,	 I/O Standard: 2.5 V,	 Current Strength: Default
// power[31]	=>  Location: PIN_V15,	 I/O Standard: 2.5 V,	 Current Strength: Default
// power[32]	=>  Location: PIN_W16,	 I/O Standard: 2.5 V,	 Current Strength: Default
// power[33]	=>  Location: PIN_P2,	 I/O Standard: 2.5 V,	 Current Strength: Default
// power[34]	=>  Location: PIN_D16,	 I/O Standard: 2.5 V,	 Current Strength: Default
// power[35]	=>  Location: PIN_AA16,	 I/O Standard: 2.5 V,	 Current Strength: Default
// power[36]	=>  Location: PIN_A16,	 I/O Standard: 2.5 V,	 Current Strength: Default
// y_out[0]	=>  Location: PIN_R20,	 I/O Standard: 2.5 V,	 Current Strength: Default
// y_out[1]	=>  Location: PIN_L4,	 I/O Standard: 2.5 V,	 Current Strength: Default
// y_out[2]	=>  Location: PIN_N5,	 I/O Standard: 2.5 V,	 Current Strength: Default
// y_out[3]	=>  Location: PIN_Y14,	 I/O Standard: 2.5 V,	 Current Strength: Default
// y_out[4]	=>  Location: PIN_J1,	 I/O Standard: 2.5 V,	 Current Strength: Default
// y_out[5]	=>  Location: PIN_AB7,	 I/O Standard: 2.5 V,	 Current Strength: Default
// y_out[6]	=>  Location: PIN_K21,	 I/O Standard: 2.5 V,	 Current Strength: Default
// y_out[7]	=>  Location: PIN_H3,	 I/O Standard: 2.5 V,	 Current Strength: Default
// y_out[8]	=>  Location: PIN_P1,	 I/O Standard: 2.5 V,	 Current Strength: Default
// y_out[9]	=>  Location: PIN_H2,	 I/O Standard: 2.5 V,	 Current Strength: Default
// y_out[10]	=>  Location: PIN_T3,	 I/O Standard: 2.5 V,	 Current Strength: Default
// y_out[11]	=>  Location: PIN_G19,	 I/O Standard: 2.5 V,	 Current Strength: Default
// y_out[12]	=>  Location: PIN_N3,	 I/O Standard: 2.5 V,	 Current Strength: Default
// y_out[13]	=>  Location: PIN_F1,	 I/O Standard: 2.5 V,	 Current Strength: Default
// y_out[14]	=>  Location: PIN_L16,	 I/O Standard: 2.5 V,	 Current Strength: Default
// y_out[15]	=>  Location: PIN_G3,	 I/O Standard: 2.5 V,	 Current Strength: Default
// x_in[1]	=>  Location: PIN_N1,	 I/O Standard: 2.5 V,	 Current Strength: Default
// x_in[0]	=>  Location: PIN_M20,	 I/O Standard: 2.5 V,	 Current Strength: Default
// x_in[2]	=>  Location: PIN_M1,	 I/O Standard: 2.5 V,	 Current Strength: Default
// x_in[3]	=>  Location: PIN_L2,	 I/O Standard: 2.5 V,	 Current Strength: Default
// x_in[4]	=>  Location: PIN_J7,	 I/O Standard: 2.5 V,	 Current Strength: Default
// x_in[5]	=>  Location: PIN_M19,	 I/O Standard: 2.5 V,	 Current Strength: Default
// x_in[6]	=>  Location: PIN_E1,	 I/O Standard: 2.5 V,	 Current Strength: Default
// x_in[7]	=>  Location: PIN_F3,	 I/O Standard: 2.5 V,	 Current Strength: Default
// x_in[8]	=>  Location: PIN_J6,	 I/O Standard: 2.5 V,	 Current Strength: Default
// x_in[9]	=>  Location: PIN_L1,	 I/O Standard: 2.5 V,	 Current Strength: Default
// x_in[10]	=>  Location: PIN_F8,	 I/O Standard: 2.5 V,	 Current Strength: Default
// x_in[11]	=>  Location: PIN_G20,	 I/O Standard: 2.5 V,	 Current Strength: Default
// x_in[12]	=>  Location: PIN_G4,	 I/O Standard: 2.5 V,	 Current Strength: Default
// x_in[13]	=>  Location: PIN_M7,	 I/O Standard: 2.5 V,	 Current Strength: Default
// x_in[14]	=>  Location: PIN_H6,	 I/O Standard: 2.5 V,	 Current Strength: Default
// x_in[15]	=>  Location: PIN_K22,	 I/O Standard: 2.5 V,	 Current Strength: Default
// rst	=>  Location: PIN_L22,	 I/O Standard: 2.5 V,	 Current Strength: Default


wire gnd;
wire vcc;
wire unknown;

assign gnd = 1'b0;
assign vcc = 1'b1;
assign unknown = 1'bx;

tri1 devclrn;
tri1 devpor;
tri1 devoe;
// synopsys translate_off
initial $sdf_annotate("agc_2_1100mv_85c_v_slow.sdo");
// synopsys translate_on

wire \LessThan0~0_combout ;
wire \LessThan0~1_combout ;
wire \LessThan0~2_combout ;
wire \LessThan0~3_combout ;
wire \clk~input_o ;
wire \rst~input_o ;
wire \rst~inputclkctrl_outclk ;
wire \cnt[0]~5_combout ;
wire \Add0~2_sumout ;
wire \Add0~3 ;
wire \Add0~6_sumout ;
wire \Add0~7 ;
wire \Add0~10_sumout ;
wire \Add0~11 ;
wire \Add0~14_sumout ;
wire \Add0~15 ;
wire \Add0~18_sumout ;
wire \cnt[5]~6_combout ;
wire \Equal0~0_combout ;
wire \x_power1~0_combout ;
wire \Equal0~0clkctrl_outclk ;
wire \x_power1~1_combout ;
wire \x_power1~2_combout ;
wire \x_power1~3_combout ;
wire \x_power1~4_combout ;
wire \x_power1~5_combout ;
wire \x_power1~6_combout ;
wire \x_power1~7_combout ;
wire \x_power1~8_combout ;
wire \x_power1~9_combout ;
wire \x_power1~10_combout ;
wire \x_power1~11_combout ;
wire \x_power1~12_combout ;
wire \x_power1~13_combout ;
wire \x_power1~14_combout ;
wire \x_power1~15_combout ;
wire \x_power1~16_combout ;
wire \x_power1~17_combout ;
wire \x_power1~18_combout ;
wire \x_power1~19_combout ;
wire \x_power1~20_combout ;
wire \x_power1~21_combout ;
wire \x_power1~22_combout ;
wire \x_power1~23_combout ;
wire \x_power1~24_combout ;
wire \x_power1~25_combout ;
wire \x_power1~26_combout ;
wire \x_power1~27_combout ;
wire \x_power1~28_combout ;
wire \x_power1~29_combout ;
wire \x_power1~30_combout ;
wire \x_power1~31_combout ;
wire \x_power1~32_combout ;
wire \x_power1~33_combout ;
wire \x_power1~34_combout ;
wire \x_power1~35_combout ;
wire \x_power1~36_combout ;
wire \x_in[1]~input_o ;
wire \LessThan0~5_combout ;
wire \LessThan0~6_combout ;
wire \LessThan0~4_combout ;
wire \LessThan0~7_combout ;
wire \LessThan0~8_combout ;
wire \y_out~0_combout ;
wire \x_in[2]~input_o ;
wire \x_in[0]~input_o ;
wire \y_out~1_combout ;
wire \x_in[3]~input_o ;
wire \y_out~2_combout ;
wire \x_in[4]~input_o ;
wire \y_out~3_combout ;
wire \x_in[5]~input_o ;
wire \y_out~4_combout ;
wire \x_in[6]~input_o ;
wire \y_out~5_combout ;
wire \x_in[7]~input_o ;
wire \y_out~6_combout ;
wire \x_in[8]~input_o ;
wire \y_out~7_combout ;
wire \x_in[9]~input_o ;
wire \y_out~8_combout ;
wire \x_in[10]~input_o ;
wire \y_out~9_combout ;
wire \x_in[11]~input_o ;
wire \y_out~10_combout ;
wire \x_in[12]~input_o ;
wire \y_out~11_combout ;
wire \x_in[13]~input_o ;
wire \y_out~12_combout ;
wire \x_in[14]~input_o ;
wire \y_out~13_combout ;
wire \x_in[15]~input_o ;
wire \y_out~14_combout ;
wire \y_out~15_combout ;
wire [36:0] x_power;
wire [36:0] x_power1;


// Location: MLABCELL_X10_Y24_N22
stratixiii_lcell_comb \LessThan0~0 (
// Equation(s):
// \LessThan0~0_combout  = (!x_power[2] & !x_power[1])

	.dataa(gnd),
	.datab(gnd),
	.datac(!x_power[2]),
	.datad(!x_power[1]),
	.datae(gnd),
	.dataf(gnd),
	.datag(gnd),
	.cin(gnd),
	.sharein(gnd),
	.combout(\LessThan0~0_combout ),
	.sumout(),
	.cout(),
	.shareout());
// synopsys translate_off
defparam \LessThan0~0 .extended_lut = "off";
defparam \LessThan0~0 .lut_mask = 64'hF000F000F000F000;
defparam \LessThan0~0 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X10_Y24_N24
stratixiii_lcell_comb \LessThan0~1 (
// Equation(s):
// \LessThan0~1_combout  = ( x_power[6] & ( (x_power[4] & (x_power[5] & (x_power[3] & x_power[7]))) ) )

	.dataa(!x_power[4]),
	.datab(!x_power[5]),
	.datac(!x_power[3]),
	.datad(!x_power[7]),
	.datae(gnd),
	.dataf(!x_power[6]),
	.datag(gnd),
	.cin(gnd),
	.sharein(gnd),
	.combout(\LessThan0~1_combout ),
	.sumout(),
	.cout(),
	.shareout());
// synopsys translate_off
defparam \LessThan0~1 .extended_lut = "off";
defparam \LessThan0~1 .lut_mask = 64'h0000000000010001;
defparam \LessThan0~1 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X10_Y24_N28
stratixiii_lcell_comb \LessThan0~2 (
// Equation(s):
// \LessThan0~2_combout  = ( x_power[11] & ( (x_power[12] & (x_power[15] & (x_power[14] & x_power[13]))) ) )

	.dataa(!x_power[12]),
	.datab(!x_power[15]),
	.datac(!x_power[14]),
	.datad(!x_power[13]),
	.datae(gnd),
	.dataf(!x_power[11]),
	.datag(gnd),
	.cin(gnd),
	.sharein(gnd),
	.combout(\LessThan0~2_combout ),
	.sumout(),
	.cout(),
	.shareout());
// synopsys translate_off
defparam \LessThan0~2 .extended_lut = "off";
defparam \LessThan0~2 .lut_mask = 64'h0000000000010001;
defparam \LessThan0~2 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X10_Y24_N32
stratixiii_lcell_comb \LessThan0~3 (
// Equation(s):
// \LessThan0~3_combout  = ( \LessThan0~0_combout  & ( x_power[8] & ( (\LessThan0~2_combout  & ((x_power[9]) # (x_power[10]))) ) ) ) # ( !\LessThan0~0_combout  & ( x_power[8] & ( (\LessThan0~2_combout  & ((x_power[9]) # (x_power[10]))) ) ) ) # ( 
// \LessThan0~0_combout  & ( !x_power[8] & ( (\LessThan0~2_combout  & x_power[10]) ) ) ) # ( !\LessThan0~0_combout  & ( !x_power[8] & ( (\LessThan0~2_combout  & (((\LessThan0~1_combout  & x_power[9])) # (x_power[10]))) ) ) )

	.dataa(!\LessThan0~2_combout ),
	.datab(!x_power[10]),
	.datac(!\LessThan0~1_combout ),
	.datad(!x_power[9]),
	.datae(!\LessThan0~0_combout ),
	.dataf(!x_power[8]),
	.datag(gnd),
	.cin(gnd),
	.sharein(gnd),
	.combout(\LessThan0~3_combout ),
	.sumout(),
	.cout(),
	.shareout());
// synopsys translate_off
defparam \LessThan0~3 .extended_lut = "off";
defparam \LessThan0~3 .lut_mask = 64'h1115111111551155;
defparam \LessThan0~3 .shared_arith = "off";
// synopsys translate_on

// Location: IOOBUF_X0_Y20_N20
stratixiii_io_obuf \power[0]~output (
	.i(x_power[0]),
	.oe(vcc),
	.dynamicterminationcontrol(gnd),
	.seriesterminationcontrol(14'b00000000000000),
	.parallelterminationcontrol(14'b00000000000000),
	.devoe(devoe),
	.o(power[0]),
	.obar());
// synopsys translate_off
defparam \power[0]~output .bus_hold = "false";
defparam \power[0]~output .open_drain_output = "false";
defparam \power[0]~output .shift_series_termination_control = "false";
// synopsys translate_on

// Location: IOOBUF_X0_Y11_N82
stratixiii_io_obuf \power[1]~output (
	.i(x_power[1]),
	.oe(vcc),
	.dynamicterminationcontrol(gnd),
	.seriesterminationcontrol(14'b00000000000000),
	.parallelterminationcontrol(14'b00000000000000),
	.devoe(devoe),
	.o(power[1]),
	.obar());
// synopsys translate_off
defparam \power[1]~output .bus_hold = "false";
defparam \power[1]~output .open_drain_output = "false";
defparam \power[1]~output .shift_series_termination_control = "false";
// synopsys translate_on

// Location: IOOBUF_X53_Y22_N95
stratixiii_io_obuf \power[2]~output (
	.i(x_power[2]),
	.oe(vcc),
	.dynamicterminationcontrol(gnd),
	.seriesterminationcontrol(14'b00000000000000),
	.parallelterminationcontrol(14'b00000000000000),
	.devoe(devoe),
	.o(power[2]),
	.obar());
// synopsys translate_off
defparam \power[2]~output .bus_hold = "false";
defparam \power[2]~output .open_drain_output = "false";
defparam \power[2]~output .shift_series_termination_control = "false";
// synopsys translate_on

// Location: IOOBUF_X53_Y21_N82
stratixiii_io_obuf \power[3]~output (
	.i(x_power[3]),
	.oe(vcc),
	.dynamicterminationcontrol(gnd),
	.seriesterminationcontrol(14'b00000000000000),
	.parallelterminationcontrol(14'b00000000000000),
	.devoe(devoe),
	.o(power[3]),
	.obar());
// synopsys translate_off
defparam \power[3]~output .bus_hold = "false";
defparam \power[3]~output .open_drain_output = "false";
defparam \power[3]~output .shift_series_termination_control = "false";
// synopsys translate_on

// Location: IOOBUF_X53_Y8_N51
stratixiii_io_obuf \power[4]~output (
	.i(x_power[4]),
	.oe(vcc),
	.dynamicterminationcontrol(gnd),
	.seriesterminationcontrol(14'b00000000000000),
	.parallelterminationcontrol(14'b00000000000000),
	.devoe(devoe),
	.o(power[4]),
	.obar());
// synopsys translate_off
defparam \power[4]~output .bus_hold = "false";
defparam \power[4]~output .open_drain_output = "false";
defparam \power[4]~output .shift_series_termination_control = "false";
// synopsys translate_on

// Location: IOOBUF_X0_Y22_N33
stratixiii_io_obuf \power[5]~output (
	.i(x_power[5]),
	.oe(vcc),
	.dynamicterminationcontrol(gnd),
	.seriesterminationcontrol(14'b00000000000000),
	.parallelterminationcontrol(14'b00000000000000),
	.devoe(devoe),