keyled.syr

一个在xilinx公司ise编译环境下仿真成功的键盘操作程序。

Release 4.1WP3.x - xst E.33
Copyright (c) 1995-2001 Xilinx, Inc.  All rights reserved.
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--> Parameter overwrite set to YES
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--> =========================================================================
---- Source Parameters
Input Format                       : VERILOG
Input File Name                    : keyled.prj

---- Target Parameters
Target Device                      : xc2s100-pq208-5
Output File Name                   : keyled
Output Format                      : NGC
Target Technology                  : spartan2

---- Source Options
Top Module Name                    : keyled
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
FSM Flip-Flop Type                 : D
Mux Extraction                     : YES
Resource Sharing                   : YES
Complex Clock Enable Extraction    : YES
ROM Extraction                     : Yes
RAM Extraction                     : Yes
RAM Style                          : Auto
Mux Style                          : Auto
Decoder Extraction                 : YES
Priority Encoder Extraction        : YES
Shift Register Extraction          : YES
Logical Shifter Extraction         : YES
XOR Collapsing                     : YES
Automatic Register Balancing       : No

---- Target Options
Add IO Buffers                     : YES
Equivalent register Removal        : YES
Add Generic Clock Buffer(BUFG)     : 4
Global Maximum Fanout              : 100
Register Duplication               : YES
Move First FlipFlop Stage          : YES
Move Last FlipFlop Stage           : YES
Slice Packing                      : YES
Pack IO Registers into IOBs        : auto
Speed Grade                        : 5

---- General Options
Optimization Criterion             : Speed
Optimization Effort                : 1
Check Attribute Syntax             : YES
Keep Hierarchy                     : No
Global Optimization                : AllClockNets
Write Timing Constraints           : No
Incremental Synthesis              : NO

=========================================================================

 
Compiling source file : keyled.prj
Compiling included source file 'key.v'
Module <keyled> compiled.
Continuing compilation of source file 'keyled.prj'
Compiling included source file 'd:/xilinx_webpack/verilog/src/iSE/unisim_comp.v'
Continuing compilation of source file 'keyled.prj'
No errors in compilation
Analysis of file <keyled.prj> succeeded.
 
 
Starting Verilog synthesis.
 
Analyzing top module <keyled>.
WARNING:Xst:905 - "key.v", line 9: The signals <keyin> are missing in the sensitivity list of always block.
Module <keyled> is correct for synthesis.

Synthesizing Unit <keyled>.
    Related source file is key.v.
Unit <keyled> synthesized.

=========================================================================
HDL Synthesis Report

Found no macro
=========================================================================


Starting low level synthesis...
Optimizing unit <keyled> ...

Building and optimizing final netlist ...

=========================================================================
Final Results
Top Level Output File Name         : keyled
Output Format                      : NGC
Optimization Criterion             : Speed
Target Technology                  : spartan2
Keep Hierarchy                     : No
Macro Generator                    : macro+

Design Statistics
# IOs                              : 16

Cell Usage :
# IO Buffers                       : 16
#      IBUF                        : 8
#      OBUF                        : 8
=========================================================================


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
No clock signals found in this design

Timing Summary:
---------------
Speed Grade: -5

   Minimum period: No path found
   Minimum input arrival time before clock: No path found
   Maximum output required time after clock: No path found
   Maximum combinational path delay: 7.631ns

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

-------------------------------------------------------------------------
Timing constraint: Default path analysis
Delay:               7.631ns (Levels of Logic = 2)
  Source:            keyin_7
  Destination:       ledout_7

  Data Path: keyin_7 to ledout_7
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
    IBUF:I->O              1   0.924   1.150  keyin_7_IBUF (ledout_7_OBUF)
    OBUF:I->O                  5.557          ledout_7_OBUF (ledout_7)
    ----------------------------------------
    Total                      7.631ns (6.481ns logic, 1.150ns route)
                                       (84.9% logic, 15.1% route)

=========================================================================
CPU : 1.15 / 1.26 s | Elapsed : 1.00 / 1.00 s
 
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