key2.syr

一个在xilinx公司ise编译环境下仿真成功的键盘操作程序。

Release 4.1WP3.x - xst E.33
Copyright (c) 1995-2001 Xilinx, Inc.  All rights reserved.
--> Parameter TMPDIR set to .
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--> Parameter overwrite set to YES
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--> =========================================================================
---- Source Parameters
Input Format                       : VERILOG
Input File Name                    : key2.prj

---- Target Parameters
Target Device                      : xc2s100-pq208-5
Output File Name                   : key2
Output Format                      : NGC
Target Technology                  : spartan2

---- Source Options
Top Module Name                    : key2
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
FSM Flip-Flop Type                 : D
Mux Extraction                     : YES
Resource Sharing                   : YES
Complex Clock Enable Extraction    : YES
ROM Extraction                     : Yes
RAM Extraction                     : Yes
RAM Style                          : Auto
Mux Style                          : Auto
Decoder Extraction                 : YES
Priority Encoder Extraction        : YES
Shift Register Extraction          : YES
Logical Shifter Extraction         : YES
XOR Collapsing                     : YES
Automatic Register Balancing       : No

---- Target Options
Add IO Buffers                     : YES
Equivalent register Removal        : YES
Add Generic Clock Buffer(BUFG)     : 4
Global Maximum Fanout              : 100
Register Duplication               : YES
Move First FlipFlop Stage          : YES
Move Last FlipFlop Stage           : YES
Slice Packing                      : YES
Pack IO Registers into IOBs        : auto
Speed Grade                        : 5

---- General Options
Optimization Criterion             : Speed
Optimization Effort                : 1
Check Attribute Syntax             : YES
Keep Hierarchy                     : No
Global Optimization                : AllClockNets
Write Timing Constraints           : No
Incremental Synthesis              : NO

=========================================================================

 
Compiling source file : key2.prj
Compiling included source file 'key2.v'
Module <key2> compiled.
Continuing compilation of source file 'key2.prj'
Compiling included source file 'd:/xilinx_webpack/verilog/src/iSE/unisim_comp.v'
Continuing compilation of source file 'key2.prj'
No errors in compilation
Analysis of file <key2.prj> succeeded.
 
 
Starting Verilog synthesis.
 
Analyzing top module <key2>.
Module <key2> is correct for synthesis.

Synthesizing Unit <key2>.
    Related source file is key2.v.
WARNING:Xst:646 - Signal <buffer> is assigned but never used.
Unit <key2> synthesized.

=========================================================================
HDL Synthesis Report

Found no macro
=========================================================================


Starting low level synthesis...
Optimizing unit <key2> ...

Building and optimizing final netlist ...

=========================================================================
Final Results
Top Level Output File Name         : key2
Output Format                      : NGC
Optimization Criterion             : Speed
Target Technology                  : spartan2
Keep Hierarchy                     : No
Macro Generator                    : macro+

Design Statistics
# IOs                              : 16

Cell Usage :
# BELS                             : 21
#      LUT2                        : 3
#      LUT3                        : 7
#      LUT4                        : 11
# IO Buffers                       : 16
#      IBUF                        : 8
#      OBUF                        : 8
=========================================================================


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
No clock signals found in this design

Timing Summary:
---------------
Speed Grade: -5

   Minimum period: No path found
   Minimum input arrival time before clock: No path found
   Maximum output required time after clock: No path found
   Maximum combinational path delay: 18.136ns

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

-------------------------------------------------------------------------
Timing constraint: Default path analysis
Delay:               18.136ns (Levels of Logic = 7)
  Source:            keyin_5
  Destination:       ledout_1

  Data Path: keyin_5 to ledout_1
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
    IBUF:I->O              4   0.924   1.600  keyin_5_IBUF (keyin_5_IBUF)
    LUT3:I0->O             3   0.653   1.480  I_SF25 (N32)
    LUT3:I2->O             3   0.653   1.480  I_SF27 (N34)
    LUT3:I1->O             2   0.653   1.340  I_SF18 (N58)
    LUT4:I3->O             2   0.653   1.340  I_SF17 (N60)
    LUT2:I0->O             1   0.653   1.150  I_ledout_1 (ledout_1_OBUF)
    OBUF:I->O                  5.557          ledout_1_OBUF (ledout_1)
    ----------------------------------------
    Total                     18.136ns (9.746ns logic, 8.390ns route)
                                       (53.7% logic, 46.3% route)

=========================================================================
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