📄 keyled.mrp
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Release 4.1WP3.x - Map E.33Xilinx Mapping Report File for Design 'keyled'Design Information------------------Command Line : map -p xc2s100-pq208-5 -cm area -k 4 -c 100 -tx off keyled.ngd Target Device : x2s100Target Package : pq208Target Speed : -5Mapper Version : spartan2 -- $Revision: 1.58 $Mapped Date : Mon Feb 17 16:22:59 2003Design Summary-------------- Number of errors: 0 Number of warnings: 0 Number of Slices: 0 out of 1,200 0% Number of Slices containing unrelated logic: 0 out of 0 0% Number of 4 input LUTs: 0 out of 2,400 0% Number of bonded IOBs: 16 out of 140 11%Total equivalent gate count for design: 0Additional JTAG gate count for IOBs: 768Table of Contents-----------------Section 1 - ErrorsSection 2 - WarningsSection 3 - InformationalSection 4 - Removed Logic SummarySection 5 - Removed LogicSection 6 - IOB PropertiesSection 7 - RPMsSection 8 - Guide ReportSection 9 - Area Group SummarySection 10 - Modular Design SummarySection 1 - Errors------------------Section 2 - Warnings--------------------Section 3 - Informational-------------------------INFO:MapLib:62 - All of the external outputs in this design are using slew rate
limited output drivers. The delay on speed critical outputs can be
dramatically reduced by designating them as fast outputs in the schematic.Section 4 - Removed Logic Summary---------------------------------Section 5 - Removed Logic-------------------------Section 6 - IOB Properties--------------------------+------------------------------------------------------------------------------------------------------------------------+| IOB Name | Type | Direction | IO Standard | Drive | Slew | Reg (s) | Resistor | IOB || | | | | Strength | Rate | | | Delay |+------------------------------------------------------------------------------------------------------------------------+| keyin<0> | IOB | INPUT | LVTTL | | | | | || keyin<1> | IOB | INPUT | LVTTL | | | | | || keyin<2> | IOB | INPUT | LVTTL | | | | | || keyin<3> | IOB | INPUT | LVTTL | | | | | || keyin<4> | IOB | INPUT | LVTTL | | | | | || keyin<5> | IOB | INPUT | LVTTL | | | | | || keyin<6> | IOB | INPUT | LVTTL | | | | | || keyin<7> | IOB | INPUT | LVTTL | | | | | || ledout<0> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || ledout<1> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || ledout<2> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || ledout<3> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || ledout<4> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || ledout<5> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || ledout<6> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || ledout<7> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | |+------------------------------------------------------------------------------------------------------------------------+Section 7 - RPMs----------------Section 8 - Guide Report------------------------Guide not run on this design.Section 9 - Area Group Summary------------------------------No area groups were found in this design.Section 10 - Modular Design Summary-----------------------------------Modular Design not used for this design.
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