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LOG
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Output Format : NGCOptimization Criterion : SpeedTarget Technology : spartan2Keep Hierarchy : NoMacro Generator : macro+Macro Statistics# ROMs : 1 16x8-bit ROM : 1# Registers : 18 30-bit register : 1 1-bit register : 17# Multiplexers : 1 4-bit 4-to-1 multiplexer : 1# Adders/Subtractors : 5 4-bit adder : 4 30-bit adder : 1Design Statistics# IOs : 15Cell Usage :# BELS : 182# GND : 1# LUT1 : 23# LUT1_D : 1# LUT1_L : 21# LUT2 : 10# LUT3 : 10# LUT4 : 25# LUT4_D : 1# LUT4_L : 1# MUXCY : 41# MUXF5 : 6# VCC : 1# XORCY : 41# FlipFlops/Latches : 48# FDE_1 : 1# FDR_1 : 30# FDRE_1 : 16# LD : 1# Clock Buffers : 1# BUFGP : 1# IO Buffers : 14# IBUF : 2# OBUF : 12==================================================================================================================================================TIMING REPORTNOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE. FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT GENERATED AFTER PLACE-and-ROUTE.Clock Information:-----------------------------------------------------+------------------------+-------+Clock Signal | Clock buffer(FF name) | Load |-----------------------------------+------------------------+-------+sec:Q | NONE | 19 |clk | BUFGP | 31 |I__n0006:O | NONE(*)(keyen_reg) | 1 |-----------------------------------+------------------------+-------+(*) This 1 clock signal(s) are generated by combinatorial logic,and XST is not able to identify which are the primary clock signals.Please use the CLOCK_SIGNAL constraint to specify the clock signal(s) generated by combinatorial logic.Timing Summary:---------------Speed Grade: -6 Minimum period: 13.986ns (Maximum Frequency: 71.500MHz) Minimum input arrival time before clock: 5.479ns Maximum output required time after clock: 13.970ns Maximum combinational path delay: No path foundTiming Detail:--------------All values displayed in nanoseconds (ns)-------------------------------------------------------------------------Timing constraint: Default period analysis for Clock 'clk'Delay: 13.986ns (Levels of Logic = 24) Source: count_10 Destination: count_25 Source Clock: clk falling Destination Clock: clk falling Data Path: count_10 to count_25 Gate Net Cell:in->out fanout Delay Delay Logical Name (Net Name) ---------------------------------------- ------------ FDR_1:C->Q 14 1.085 2.340 count_10 (count_10) LUT1_L:I0->LO 1 0.549 0.000 count_101 (count_101) MUXCY:S->O 1 0.659 0.000 Madd__old_count_1_inst_cy_14 (Madd__old_count_1_inst_cy_14) MUXCY:CI->O 1 0.042 0.000 Madd__old_count_1_inst_cy_15 (Madd__old_count_1_inst_cy_15) MUXCY:CI->O 1 0.042 0.000 Madd__old_count_1_inst_cy_16 (Madd__old_count_1_inst_cy_16) MUXCY:CI->O 1 0.042 0.000 Madd__old_count_1_inst_cy_17 (Madd__old_count_1_inst_cy_17) MUXCY:CI->O 1 0.042 0.000 Madd__old_count_1_inst_cy_18 (Madd__old_count_1_inst_cy_18) MUXCY:CI->O 1 0.042 0.000 Madd__old_count_1_inst_cy_19 (Madd__old_count_1_inst_cy_19) MUXCY:CI->O 1 0.042 0.000 Madd__old_count_1_inst_cy_20 (Madd__old_count_1_inst_cy_20) MUXCY:CI->O 1 0.042 0.000 Madd__old_count_1_inst_cy_21 (Madd__old_count_1_inst_cy_21) MUXCY:CI->O 1 0.042 0.000 Madd__old_count_1_inst_cy_22 (Madd__old_count_1_inst_cy_22) MUXCY:CI->O 1 0.042 0.000 Madd__old_count_1_inst_cy_23 (Madd__old_count_1_inst_cy_23) MUXCY:CI->O 1 0.042 0.000 Madd__old_count_1_inst_cy_24 (Madd__old_count_1_inst_cy_24) MUXCY:CI->O 1 0.042 0.000 Madd__old_count_1_inst_cy_25 (Madd__old_count_1_inst_cy_25) MUXCY:CI->O 1 0.042 0.000 Madd__old_count_1_inst_cy_26 (Madd__old_count_1_inst_cy_26) MUXCY:CI->O 1 0.042 0.000 Madd__old_count_1_inst_cy_27 (Madd__old_count_1_inst_cy_27) MUXCY:CI->O 1 0.042 0.000 Madd__old_count_1_inst_cy_28 (Madd__old_count_1_inst_cy_28) MUXCY:CI->O 1 0.042 0.000 Madd__old_count_1_inst_cy_29 (Madd__old_count_1_inst_cy_29) MUXCY:CI->O 1 0.042 0.000 Madd__old_count_1_inst_cy_30 (Madd__old_count_1_inst_cy_30) MUXCY:CI->O 1 0.042 0.000 Madd__old_count_1_inst_cy_31 (Madd__old_count_1_inst_cy_31) MUXCY:CI->O 0 0.042 0.000 Madd__old_count_1_inst_cy_32 (Madd__old_count_1_inst_cy_32) XORCY:CI->O 2 0.420 1.206 Madd__old_count_1_inst_sum_33 (N167) LUT2:I1->O 1 0.549 1.035 I_1_LUT_8 (N169) LUT4_D:I0->O 1 0.549 1.035 I_0_LUT_10 (N201) LUT2:I0->O 16 0.549 2.520 I__n0004 (N245) FDR_1:R 0.734 count_25 ---------------------------------------- Total 13.986ns (5.850ns logic, 8.136ns route) (41.8% logic, 58.2% route)-------------------------------------------------------------------------Timing constraint: Default OFFSET IN BEFORE for Clock 'sec:Q'Offset: 5.479ns (Levels of Logic = 3) Source: keyclr Destination: min_0 Destination Clock: sec:Q falling Data Path: keyclr to min_0 Gate Net Cell:in->out fanout Delay Delay Logical Name (Net Name) ---------------------------------------- ------------ IBUF:I->O 6 0.776 1.665 keyclr_IBUF (keyclr_IBUF) LUT1:I0->O 1 0.549 0.000 I__n0014_F (N1359) MUXF5:I0->O 4 0.315 1.440 I__n0014 (N261) FDRE_1:R 0.734 min_0 ---------------------------------------- Total 5.479ns (2.374ns logic, 3.105ns route) (43.3% logic, 56.7% route)-------------------------------------------------------------------------Timing constraint: Default OFFSET OUT AFTER for Clock 'clk'Offset: 13.970ns (Levels of Logic = 5) Source: count_10 Destination: lddat_7 Source Clock: clk falling Data Path: count_10 to lddat_7 Gate Net Cell:in->out fanout Delay Delay Logical Name (Net Name) ---------------------------------------- ------------ FDR_1:C->Q 14 1.085 2.340 count_10 (count_10) LUT3:I2->O 1 0.549 0.000 Mmux_ledbuf_inst_lut3_0 (Mmux_ledbuf_xstmacro_int_tempname0) MUXF5:I0->O 8 0.315 1.845 Mmux_ledbuf_inst_mux_f5_0 (N359) LUT4:I0->O 1 0.549 1.035 Mrom__inst_lut4_7 (N145) LUT4:I0->O 1 0.549 1.035 I_lddat_7 (lddat_7_OBUF) OBUF:I->O 4.668 lddat_7_OBUF (lddat_7) ---------------------------------------- Total 13.970ns (7.715ns logic, 6.255ns route) (55.2% logic, 44.8% route)=========================================================================CPU : 3.95 / 4.06 s | Elapsed : 4.00 / 4.00 s --> EXEWRAP detected that program 'D:/xilinx_webpack/bin/nt/xst.exe' completed successfully.Done: completed successfully.
Starting: 'exewrap @__ednTOngd_exewrap.rsp'
Starting: 'ngdbuild -f __ngdbuild.rsp 'Release 4.1WP3.x - ngdbuild E.33Copyright (c) 1995-2001 Xilinx, Inc. All rights reserved.ERROR:Portability:138 - Invalid file format, check the command argument file "__ngdbuild.rsp".Usage: ngdbuild [-p <partname>] {-sd <source_dir>} {-l <library>} [-ur<rules_file[.urf]>] [-dd <output_dir>] [-r] [-a] [-u] [-nt timestamp|on|off][-uc <ucf_file[.ucf]>] [-aul] [-i] [-modular initial|module|assemble] [-quiet][-verbose] [-active <active_module_name>] [-pimpath <pimpath>] {-use_pim<pim_module_name>} <design_name> [<ngd_file[.ngd]>] -p partname Use specified part type to implement the design -sd source_dir Add "source_dir" to the list of directories to search when resolving netlist file references -l library Add "library" to the list of source libraries passed to the netlisters -ur rules_file User rules file for netlist launcher -dd output_dir Directory to place intermediate .ngo files -nt value NGO file generation Options: "timestamp", "on", "off" -nt timestamp: Regenerate NGO only when source netlist is newer than existing NGO file (default) -nt on: Always regenerate NGO file from source design netlists -nt off: Do not regenerate NGO files which already exist. Build NGD file from existing NGO files -uc ucf_file Use specified "User Constraint File". The file <design_name>.ucf is used by default if it is found in the local directory. -r Ignore location constraints -aul Allow unmatched LOC constraints -a Infer pad components from ports in top-level EDIF netlist (if any) -i Ignore usage of default ucf file, if present -u Allow unexpanded blocks in output NGD design. During partial design assembly flow, it gets used along with -modular assemble switch to consider unexpanded blocks as unimplemented modules. -modular initial|module|assemble Modular design flows: -modular initial Modular design in initial budgeting mode -modular module -active <active_module_name> Modular design in active module mode -active <active_module_name> Specifies the name of active module. -modular assemble -pimpath <pimpath> -use_pim <pim_module_name> Modular design in assembly mode -pimpath <pimpath> Specifies directory contains PIMs. -use_pim <pim_module_name> Specifies an instantiated module in a top level design. -use_pim can be used multiple times to specify multiple instantiated modules. if -use_pim is missing, all subdirectories located in <pimpath> directory, which contain a .ngo file with the same subdirectory name, will be considered as valid instantiated modules. -quiet Only report Warning and Error messages -verbose Reports all messagesNGDBUILD: Translates and merges the various source files of a design into asingle "NGD" design database.EXEWRAP detected a return code of '2' from program 'ngdbuild'Done: failed with exit code: 0002.
ISE Auto-Make Log File-----------------------
Starting: 'jhdparse @_clock.jp'
JHDPARSE - VHDL/Verilog Parser.
ISE 4.1i Copyright(c) 1999-2001 Xilinx, Inc. All rights reserved.
Scanning d:/xilinx_webpack/data/simprim.lst
Scanning d:/xilinx_webpack/verilog/src/iSE/unisim_comp.v
Scanning clock.v
Writing clock.jhd.
JHDPARSE complete - 0 errors, 0 warnings.
Done: completed successfully.
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