clock.syr

在xilinx的ise环境下用vhdl编写的一个时钟程序。

Release 4.1WP3.x - xst E.33
Copyright (c) 1995-2001 Xilinx, Inc.  All rights reserved.
--> Parameter TMPDIR set to .
CPU : 0.00 / 0.11 s | Elapsed : 0.00 / 0.00 s
 
--> Parameter overwrite set to YES
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--> =========================================================================
---- Source Parameters
Input Format                       : VERILOG
Input File Name                    : clock.prj

---- Target Parameters
Target Device                      : xc2s100-pq208-5
Output File Name                   : clock
Output Format                      : NGC
Target Technology                  : spartan2

---- Source Options
Top Module Name                    : clock
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
FSM Flip-Flop Type                 : D
Mux Extraction                     : YES
Resource Sharing                   : YES
Complex Clock Enable Extraction    : YES
ROM Extraction                     : Yes
RAM Extraction                     : Yes
RAM Style                          : Auto
Mux Style                          : Auto
Decoder Extraction                 : YES
Priority Encoder Extraction        : YES
Shift Register Extraction          : YES
Logical Shifter Extraction         : YES
XOR Collapsing                     : YES
Automatic Register Balancing       : No

---- Target Options
Add IO Buffers                     : YES
Equivalent register Removal        : YES
Add Generic Clock Buffer(BUFG)     : 4
Global Maximum Fanout              : 100
Register Duplication               : YES
Move First FlipFlop Stage          : YES
Move Last FlipFlop Stage           : YES
Slice Packing                      : YES
Pack IO Registers into IOBs        : auto
Speed Grade                        : 5

---- General Options
Optimization Criterion             : Speed
Optimization Effort                : 1
Check Attribute Syntax             : YES
Keep Hierarchy                     : No
Global Optimization                : AllClockNets
Write Timing Constraints           : No
Incremental Synthesis              : NO

=========================================================================

 
Compiling source file : clock.prj
Compiling included source file 'clock.v'
Module <clock> compiled.
Continuing compilation of source file 'clock.prj'
Compiling included source file 'd:/xilinx_webpack/verilog/src/iSE/unisim_comp.v'
Continuing compilation of source file 'clock.prj'
No errors in compilation
Analysis of file <clock.prj> succeeded.
 
 
Starting Verilog synthesis.
 
Analyzing top module <clock>.
WARNING:Xst:854 - "clock.v", line 12: Ignored initial statement.
WARNING:Xst:905 - "clock.v", line 30: The signals <sec> are missing in the sensitivity list of always block.
WARNING:Xst:905 - "clock.v", line 36: The signals <min> are missing in the sensitivity list of always block.
WARNING:Xst:905 - "clock.v", line 46: The signals <count, sec> are missing in the sensitivity list of always block.
Module <clock> is correct for synthesis.

Synthesizing Unit <clock>.
    Related source file is clock.v.
WARNING:Xst:737 - Found 1-bit latch for signal <keyen_reg>.
    Found 16x8-bit ROM for internal node.
    Found 4-bit adder for signal <$n0000> created at line 85.
    Found 4-bit adder for signal <$n0001> created at line 89.
    Found 4-bit adder for signal <$n0002> created at line 93.
    Found 4-bit adder for signal <$n0003> created at line 97.
    Found 30-bit adder for signal <$old_count_1>.
    Found 30-bit register for signal <count>.
    Found 4-bit 4-to-1 multiplexer for signal <ledbuf>.
    Found 16-bit register for signal <min>.
    Found 1-bit register for signal <sec>.
    Found 8 1-bit 2-to-1 multiplexers.
    Summary:
	inferred   1 ROM(s).
	inferred  47 D-type flip-flop(s).
	inferred   1 Latch(s).
	inferred   5 Adder/Subtracter(s).
	inferred  12 Multiplexer(s).
Unit <clock> synthesized.

=========================================================================
HDL Synthesis Report

Macro Statistics
# ROMs                             : 1
  16x8-bit ROM                     : 1
# Registers                        : 18
  30-bit register                  : 1
  1-bit register                   : 17
# Latches                          : 1
  1-bit latch                      : 1
# Multiplexers                     : 2
  4-bit 4-to-1 multiplexer         : 1
  2-to-1 multiplexer               : 1
# Adders/Subtractors               : 5
  4-bit adder                      : 4
  30-bit adder                     : 1

=========================================================================


Starting low level synthesis...
Optimizing unit <clock> ...

Building and optimizing final netlist ...

=========================================================================
Final Results
Top Level Output File Name         : clock
Output Format                      : NGC
Optimization Criterion             : Speed
Target Technology                  : spartan2
Keep Hierarchy                     : No
Macro Generator                    : macro+

Macro Statistics
# ROMs                             : 1
  16x8-bit ROM                     : 1
# Registers                        : 18
  30-bit register                  : 1
  1-bit register                   : 17
# Multiplexers                     : 1
  4-bit 4-to-1 multiplexer         : 1
# Adders/Subtractors               : 5
  4-bit adder                      : 4
  30-bit adder                     : 1

Design Statistics
# IOs                              : 15

Cell Usage :
# BELS                             : 178
#      GND                         : 1
#      LUT1                        : 27
#      LUT1_D                      : 1
#      LUT1_L                      : 16
#      LUT2                        : 11
#      LUT3                        : 10
#      LUT4                        : 22
#      LUT4_D                      : 1
#      LUT4_L                      : 1
#      MUXCY                       : 41
#      MUXF5                       : 5
#      VCC                         : 1
#      XORCY                       : 41
# FlipFlops/Latches                : 48
#      FDE_1                       : 1
#      FDR_1                       : 30
#      FDRE_1                      : 16
#      LD                          : 1
# Clock Buffers                    : 1
#      BUFGP                       : 1
# IO Buffers                       : 14
#      IBUF                        : 2
#      OBUF                        : 12
=========================================================================


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
sec:Q                              | NONE                   | 19    |
clk                                | BUFGP                  | 31    |
I__n0006:O                         | NONE(*)(keyen_reg)     | 1     |
-----------------------------------+------------------------+-------+
(*) This 1 clock signal(s) are generated by combinatorial logic,
and XST is not able to identify which are the primary clock signals.
Please use the CLOCK_SIGNAL constraint to specify the clock signal(s) generated by combinatorial logic.

Timing Summary:
---------------
Speed Grade: -5

   Minimum period: 15.911ns (Maximum Frequency: 62.850MHz)
   Minimum input arrival time before clock: 6.075ns
   Maximum output required time after clock: 16.133ns
   Maximum combinational path delay: No path found

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'clk'
Delay:               15.911ns (Levels of Logic = 24)
  Source:            count_10
  Destination:       count_25
  Source Clock:      clk falling
  Destination Clock: clk falling

  Data Path: count_10 to count_25
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
    FDR_1:C->Q            14   1.292   2.600  count_10 (count_10)
    LUT1_L:I0->LO          1   0.653   0.000  count_101 (count_101)
    MUXCY:S->O             1   0.784   0.000  Madd__old_count_1_inst_cy_14 (Madd__old_count_1_inst_cy_14)
    MUXCY:CI->O            1   0.050   0.000  Madd__old_count_1_inst_cy_15 (Madd__old_count_1_inst_cy_15)
    MUXCY:CI->O            1   0.050   0.000  Madd__old_count_1_inst_cy_16 (Madd__old_count_1_inst_cy_16)
    MUXCY:CI->O            1   0.050   0.000  Madd__old_count_1_inst_cy_17 (Madd__old_count_1_inst_cy_17)
    MUXCY:CI->O            1   0.050   0.000  Madd__old_count_1_inst_cy_18 (Madd__old_count_1_inst_cy_18)
    MUXCY:CI->O            1   0.050   0.000  Madd__old_count_1_inst_cy_19 (Madd__old_count_1_inst_cy_19)
    MUXCY:CI->O            1   0.050   0.000  Madd__old_count_1_inst_cy_20 (Madd__old_count_1_inst_cy_20)
    MUXCY:CI->O            1   0.050   0.000  Madd__old_count_1_inst_cy_21 (Madd__old_count_1_inst_cy_21)
    MUXCY:CI->O            1   0.050   0.000  Madd__old_count_1_inst_cy_22 (Madd__old_count_1_inst_cy_22)
    MUXCY:CI->O            1   0.050   0.000  Madd__old_count_1_inst_cy_23 (Madd__old_count_1_inst_cy_23)
    MUXCY:CI->O            1   0.050   0.000  Madd__old_count_1_inst_cy_24 (Madd__old_count_1_inst_cy_24)
    MUXCY:CI->O            1   0.050   0.000  Madd__old_count_1_inst_cy_25 (Madd__old_count_1_inst_cy_25)
    MUXCY:CI->O            1   0.050   0.000  Madd__old_count_1_inst_cy_26 (Madd__old_count_1_inst_cy_26)
    MUXCY:CI->O            1   0.050   0.000  Madd__old_count_1_inst_cy_27 (Madd__old_count_1_inst_cy_27)
    MUXCY:CI->O            1   0.050   0.000  Madd__old_count_1_inst_cy_28 (Madd__old_count_1_inst_cy_28)
    MUXCY:CI->O            1   0.050   0.000  Madd__old_count_1_inst_cy_29 (Madd__old_count_1_inst_cy_29)
    MUXCY:CI->O            1   0.050   0.000  Madd__old_count_1_inst_cy_30 (Madd__old_count_1_inst_cy_30)
    MUXCY:CI->O            1   0.050   0.000  Madd__old_count_1_inst_cy_31 (Madd__old_count_1_inst_cy_31)
    MUXCY:CI->O            0   0.050   0.000  Madd__old_count_1_inst_cy_32 (Madd__old_count_1_inst_cy_32)
    XORCY:CI->O            2   0.500   1.340  Madd__old_count_1_inst_sum_33 (N167)
    LUT2:I1->O             1   0.653   1.150  I_1_LUT_8 (N169)
    LUT4_D:I0->O           1   0.653   1.150  I_0_LUT_10 (N201)
    LUT2:I0->O            16   0.653   2.800  I__n0004 (N245)
    FDR_1:R                    0.783          count_25
    ----------------------------------------
    Total                     15.911ns (6.871ns logic, 9.040ns route)
                                       (43.2% logic, 56.8% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET IN BEFORE for Clock 'sec:Q'
Offset:              6.075ns (Levels of Logic = 3)
  Source:            keyclr
  Destination:       min_13
  Destination Clock: sec:Q falling

  Data Path: keyclr to min_13
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
    IBUF:I->O              5   0.924   1.740  keyclr_IBUF (keyclr_IBUF)
    LUT1:I0->O             1   0.653   0.000  I__n0008_F (N1347)
    MUXF5:I0->O            4   0.375   1.600  I__n0008 (N308)
    FDRE_1:R                   0.783          min_13
    ----------------------------------------
    Total                      6.075ns (2.735ns logic, 3.340ns route)
                                       (45.0% logic, 55.0% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET OUT AFTER for Clock 'clk'
Offset:              16.133ns (Levels of Logic = 5)
  Source:            count_10
  Destination:       lddat_7
  Source Clock:      clk falling

  Data Path: count_10 to lddat_7
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
    FDR_1:C->Q            14   1.292   2.600  count_10 (count_10)
    LUT3:I2->O             1   0.653   0.000  Mmux_ledbuf_inst_lut3_0 (Mmux_ledbuf_xstmacro_int_tempname0)
    MUXF5:I0->O            8   0.375   2.050  Mmux_ledbuf_inst_mux_f5_0 (N359)
    LUT4:I0->O             1   0.653   1.150  Mrom__inst_lut4_7 (N145)
    LUT4:I0->O             1   0.653   1.150  I_lddat_7 (lddat_7_OBUF)
    OBUF:I->O                  5.557          lddat_7_OBUF (lddat_7)
    ----------------------------------------
    Total                     16.133ns (9.183ns logic, 6.950ns route)
                                       (56.9% logic, 43.1% route)

=========================================================================
CPU : 3.90 / 4.01 s | Elapsed : 4.00 / 4.00 s
 
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