pci_target_unit.v

用verilog编写的pci——rtl级。

//////////////////////////////////////////////////////////////////////
////                                                              ////
////  File name: pci_target_unit.v                                ////
////                                                              ////
////  This file is part of the "PCI bridge" project               ////
////  http://www.opencores.org/cores/pci/                         ////
////                                                              ////
////  Author(s):                                                  ////
////      - Tadej Markovic, [e-mail]                   ////
////                                                              ////
////  All additional information is avaliable in the README.txt   ////
////  file.                                                       ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Tadej Markovic, [e-mail]       ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: pci_target_unit.v,v $
// Revision 1.16  2004/08/19 15:27:34  mihad
// Changed minimum pci image size to 256 bytes because
// of some PC system problems with size of IO images.
//
// Revision 1.15  2003/12/19 11:11:30  mihad
// Compact PCI Hot Swap support added.
// New testcases added.
// Specification updated.
// Test application changed to support WB B3 cycles.
//
// Revision 1.14  2003/10/17 09:11:52  markom
// mbist signals updated according to newest convention
//
// Revision 1.13  2003/08/21 20:55:14  tadejm
// Corrected bug when writing to FIFO (now it is registered).
//
// Revision 1.12  2003/08/08 16:36:33  tadejm
// Added 'three_left_out' to pci_pciw_fifo signaling three locations before full. Added comparison between current registered cbe and next unregistered cbe to signal wb_master whether it is allowed to performe burst or not. Due to this, I needed 'three_left_out' so that writing to pci_pciw_fifo can be registered, otherwise timing problems would occure.
//
// Revision 1.11  2003/01/27 16:49:31  mihad
// Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed.
//
// Revision 1.10  2002/10/18 03:36:37  tadejm
// Changed wrong signal name mbist_sen into mbist_ctrl_i.
//
// Revision 1.9  2002/10/17 22:51:08  tadejm
// Changed BIST signals for RAMs.
//
// Revision 1.8  2002/10/11 10:09:01  mihad
// Added additional testcase and changed rst name in BIST to trst
//
// Revision 1.7  2002/10/08 17:17:05  mihad
// Added BIST signals for RAMs.
//
// Revision 1.6  2002/09/25 15:53:52  mihad
// Removed all logic from asynchronous reset network
//
// Revision 1.5  2002/03/05 11:53:47  mihad
// Added some testcases, removed un-needed fifo signals
//
// Revision 1.4  2002/02/19 16:32:37  mihad
// Modified testbench and fixed some bugs
//
// Revision 1.3  2002/02/01 15:25:13  mihad
// Repaired a few bugs, updated specification, added test bench files and design document
//
// Revision 1.2  2001/10/05 08:14:30  mihad
// Updated all files with inclusion of timescale file for simulation purposes.
//
// Revision 1.1.1.1  2001/10/02 15:33:47  mihad
// New project directory structure
//
//

// Module instantiates and connects other modules lower in hierarcy
// PCI target unit consists of modules that together form datapath
// between external WISHBONE slaves and external PCI initiators
`include "pci_constants.v"

// synopsys translate_off
`include "timescale.v"
// synopsys translate_on

module pci_target_unit
(
    reset_in,
    wb_clock_in,
    pci_clock_in,

    pciu_wbm_adr_o,
    pciu_wbm_dat_o,
    pciu_wbm_dat_i,
    pciu_wbm_cyc_o,
    pciu_wbm_stb_o,
    pciu_wbm_we_o,
    pciu_wbm_cti_o,
    pciu_wbm_bte_o,
    pciu_wbm_sel_o,
    pciu_wbm_ack_i,
    pciu_wbm_rty_i,
    pciu_wbm_err_i,
    pciu_mem_enable_in,
    pciu_io_enable_in,
    pciu_map_in,
    pciu_pref_en_in,
    pciu_conf_data_in,
    pciu_wbw_fifo_empty_in,
    pciu_wbu_del_read_comp_pending_in,
    pciu_wbu_frame_en_in,
    pciu_bar0_in,
    pciu_bar1_in,
    pciu_bar2_in,
    pciu_bar3_in,
    pciu_bar4_in,
    pciu_bar5_in,
    pciu_am0_in,
    pciu_am1_in,
    pciu_am2_in,
    pciu_am3_in,
    pciu_am4_in,
    pciu_am5_in,
    pciu_ta0_in,
    pciu_ta1_in,
    pciu_ta2_in,
    pciu_ta3_in,
    pciu_ta4_in,
    pciu_ta5_in,
    pciu_at_en_in,
    pciu_cache_line_size_in,
    pciu_cache_lsize_not_zero_in,
    pciu_pciif_frame_in,
    pciu_pciif_irdy_in,
    pciu_pciif_idsel_in,
    pciu_pciif_frame_reg_in,
    pciu_pciif_irdy_reg_in,
    pciu_pciif_idsel_reg_in,
    pciu_pciif_ad_reg_in,
    pciu_pciif_cbe_reg_in,
    pciu_pciif_cbe_in,
    pciu_pciif_bckp_trdy_en_in,
    pciu_pciif_bckp_devsel_in,
    pciu_pciif_bckp_trdy_in,
    pciu_pciif_bckp_stop_in,
    pciu_pciif_trdy_reg_in,
    pciu_pciif_stop_reg_in,
    pciu_pciif_trdy_out,
    pciu_pciif_stop_out,
    pciu_pciif_devsel_out,
    pciu_pciif_trdy_en_out,
    pciu_pciif_stop_en_out,
    pciu_pciif_devsel_en_out,
    pciu_ad_load_out,
    pciu_ad_load_on_transfer_out,
    pciu_pciif_ad_out,
    pciu_pciif_ad_en_out,
    pciu_pciif_tabort_set_out,
    pciu_err_addr_out,
    pciu_err_bc_out,
    pciu_err_data_out,
    pciu_err_be_out,
    pciu_err_signal_out,
    pciu_err_source_out,
    pciu_err_rty_exp_out,
    pciu_conf_offset_out,
    pciu_conf_renable_out,
    pciu_conf_wenable_out,
    pciu_conf_be_out,
    pciu_conf_data_out,
    pciu_pci_drcomp_pending_out,
    pciu_pciw_fifo_empty_out

`ifdef PCI_BIST
    ,
    // debug chain signals
    mbist_si_i,       // bist scan serial in
    mbist_so_o,       // bist scan serial out
    mbist_ctrl_i        // bist chain shift control
`endif
);

`ifdef HOST
    `ifdef NO_CNF_IMAGE
        parameter pci_ba0_width = `PCI_NUM_OF_DEC_ADDR_LINES ;
    `else
        parameter pci_ba0_width = 20    ;
    `endif
`endif

`ifdef GUEST
    parameter pci_ba0_width = 20 ;
`endif

parameter pci_ba1_5_width = `PCI_NUM_OF_DEC_ADDR_LINES ;

input reset_in,
      wb_clock_in,
      pci_clock_in ;

output  [31:0]  pciu_wbm_adr_o   ;
output  [31:0]  pciu_wbm_dat_o ;
input   [31:0]  pciu_wbm_dat_i ;
output          pciu_wbm_cyc_o   ;
output          pciu_wbm_stb_o   ;
output          pciu_wbm_we_o    ;
output  [2:0]   pciu_wbm_cti_o   ;
output  [1:0]   pciu_wbm_bte_o   ;
output  [3:0]   pciu_wbm_sel_o   ;
input           pciu_wbm_ack_i   ;
input           pciu_wbm_rty_i   ;
input           pciu_wbm_err_i   ;

input           pciu_wbw_fifo_empty_in ;
input			pciu_wbu_del_read_comp_pending_in ;