pci_bridge32.v

用verilog编写的pci——rtl级。

                                                     conf_wb_img_ctrl1_out[1],
                                                     conf_wb_img_ctrl0_out[1]
                                                    };
wire    [5:0]   wbu_mrl_en_in                   =   {
                                                     conf_wb_img_ctrl5_out[0],
                                                     conf_wb_img_ctrl4_out[0],
                                                     conf_wb_img_ctrl3_out[0],
                                                     conf_wb_img_ctrl2_out[0],
                                                     conf_wb_img_ctrl1_out[0],
                                                     conf_wb_img_ctrl0_out[0]
                                                    };

wire    [5:0]   wbu_at_en_in                    =   {
                                                     conf_wb_img_ctrl5_out[2],
                                                     conf_wb_img_ctrl4_out[2],
                                                     conf_wb_img_ctrl3_out[2],
                                                     conf_wb_img_ctrl2_out[2],
                                                     conf_wb_img_ctrl1_out[2],
                                                     conf_wb_img_ctrl0_out[2]
                                                    } ;

wire            wbu_pci_drcomp_pending_in       =   pciu_pci_drcomp_pending_out ;
wire            wbu_pciw_empty_in               =   pciu_pciw_fifo_empty_out ;

`ifdef HOST
    wire    [31:0]  wbu_conf_data_in            =   conf_w_data_out ;
`else
`ifdef GUEST
    wire    [31:0]  wbu_conf_data_in            =   conf_r_data_out ;
`endif
`endif

wire   [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] wbu_bar0_in  =   conf_wb_ba0_out ;
wire   [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] wbu_bar1_in  =   conf_wb_ba1_out ;
wire   [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] wbu_bar2_in  =   conf_wb_ba2_out ;
wire   [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] wbu_bar3_in  =   conf_wb_ba3_out ;
wire   [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] wbu_bar4_in  =   conf_wb_ba4_out ;
wire   [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] wbu_bar5_in  =   conf_wb_ba5_out ;
wire   [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] wbu_am0_in   =   conf_wb_am0_out ;
wire   [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] wbu_am1_in   =   conf_wb_am1_out ;
wire   [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] wbu_am2_in   =   conf_wb_am2_out ;
wire   [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] wbu_am3_in   =   conf_wb_am3_out ;
wire   [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] wbu_am4_in   =   conf_wb_am4_out ;
wire   [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] wbu_am5_in   =   conf_wb_am5_out ;
wire   [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] wbu_ta0_in   =   conf_wb_ta0_out ;
wire   [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] wbu_ta1_in   =   conf_wb_ta1_out ;
wire   [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] wbu_ta2_in   =   conf_wb_ta2_out ;
wire   [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] wbu_ta3_in   =   conf_wb_ta3_out ;
wire   [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] wbu_ta4_in   =   conf_wb_ta4_out ;
wire   [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] wbu_ta5_in   =   conf_wb_ta5_out ;

wire    [23:0]  wbu_ccyc_addr_in                        =   conf_ccyc_addr_out ;
wire            wbu_master_enable_in                    =   conf_pci_master_enable_out ;
wire            wbu_cache_line_size_not_zero            =   conf_cache_lsize_not_zero_to_wb_out ;
wire    [7:0]   wbu_cache_line_size_in                  =   conf_cache_line_size_to_pci_out ;

wire            wbu_pciif_gnt_in                        = pci_gnt_i ;
wire            wbu_pciif_frame_in                      = in_reg_frame_out ;
wire            wbu_pciif_irdy_in                       = in_reg_irdy_out ;
wire            wbu_pciif_trdy_in                       = int_pci_trdy  ;
wire            wbu_pciif_stop_in                       = int_pci_stop  ;
wire            wbu_pciif_devsel_in                     = int_pci_devsel ;
wire    [31:0]  wbu_pciif_ad_reg_in                     = in_reg_ad_out ;
wire            wbu_pciif_trdy_reg_in                   = in_reg_trdy_out ;
wire            wbu_pciif_stop_reg_in                   = in_reg_stop_out ;
wire            wbu_pciif_devsel_reg_in                 = in_reg_devsel_out ;


wire    [7:0]   wbu_latency_tim_val_in                  = conf_latency_tim_out ;

wire            wbu_pciif_frame_en_in                   = out_bckp_frame_en_out ;
wire            wbu_pciif_frame_out_in                  = out_bckp_frame_out ;
wire            wbu_wb_init_complete_in                 = conf_wb_init_complete_out ;

pci_wb_slave_unit wishbone_slave_unit
(
    .reset_in                      (reset),
    .wb_clock_in                   (wb_clk),
    .pci_clock_in                  (pci_clk),
    .ADDR_I                        (wbu_addr_in),
    .SDATA_I                       (wbu_sdata_in),
    .SDATA_O                       (wbu_sdata_out),
    .CYC_I                         (wbu_cyc_in),
    .STB_I                         (wbu_stb_in),
    .WE_I                          (wbu_we_in),
    .SEL_I                         (wbu_sel_in),
    .ACK_O                         (wbu_ack_out),
    .RTY_O                         (wbu_rty_out),
    .ERR_O                         (wbu_err_out),
    .CAB_I                         (wbu_cab_in),
    .wbu_map_in                    (wbu_map_in),
    .wbu_pref_en_in                (wbu_pref_en_in),
    .wbu_mrl_en_in                 (wbu_mrl_en_in),
    .wbu_pci_drcomp_pending_in     (wbu_pci_drcomp_pending_in),
    .wbu_conf_data_in              (wbu_conf_data_in),
    .wbu_pciw_empty_in             (wbu_pciw_empty_in),
    .wbu_bar0_in                   (wbu_bar0_in),
    .wbu_bar1_in                   (wbu_bar1_in),
    .wbu_bar2_in                   (wbu_bar2_in),
    .wbu_bar3_in                   (wbu_bar3_in),
    .wbu_bar4_in                   (wbu_bar4_in),
    .wbu_bar5_in                   (wbu_bar5_in),
    .wbu_am0_in                    (wbu_am0_in),
    .wbu_am1_in                    (wbu_am1_in),
    .wbu_am2_in                    (wbu_am2_in),
    .wbu_am3_in                    (wbu_am3_in),
    .wbu_am4_in                    (wbu_am4_in),
    .wbu_am5_in                    (wbu_am5_in),
    .wbu_ta0_in                    (wbu_ta0_in),
    .wbu_ta1_in                    (wbu_ta1_in),
    .wbu_ta2_in                    (wbu_ta2_in),
    .wbu_ta3_in                    (wbu_ta3_in),
    .wbu_ta4_in                    (wbu_ta4_in),
    .wbu_ta5_in                    (wbu_ta5_in),
    .wbu_at_en_in                  (wbu_at_en_in),
    .wbu_ccyc_addr_in              (wbu_ccyc_addr_in),
    .wbu_master_enable_in          (wbu_master_enable_in),
    .wb_init_complete_in           (wbu_wb_init_complete_in),
    .wbu_cache_line_size_not_zero  (wbu_cache_line_size_not_zero),
    .wbu_cache_line_size_in        (wbu_cache_line_size_in),
    .wbu_pciif_gnt_in              (wbu_pciif_gnt_in),
    .wbu_pciif_frame_in            (wbu_pciif_frame_in),
    .wbu_pciif_frame_en_in         (wbu_pciif_frame_en_in),
    .wbu_pciif_frame_out_in        (wbu_pciif_frame_out_in),
    .wbu_pciif_irdy_in             (wbu_pciif_irdy_in),
    .wbu_pciif_trdy_in             (wbu_pciif_trdy_in),
    .wbu_pciif_stop_in             (wbu_pciif_stop_in),
    .wbu_pciif_devsel_in           (wbu_pciif_devsel_in),
    .wbu_pciif_ad_reg_in           (wbu_pciif_ad_reg_in),
    .wbu_pciif_req_out             (wbu_pciif_req_out),
    .wbu_pciif_frame_out           (wbu_pciif_frame_out),
    .wbu_pciif_frame_en_out        (wbu_pciif_frame_en_out),
    .wbu_pciif_frame_load_out      (wbu_pciif_frame_load_out),
    .wbu_pciif_irdy_out            (wbu_pciif_irdy_out),
    .wbu_pciif_irdy_en_out         (wbu_pciif_irdy_en_out),
    .wbu_pciif_ad_out              (wbu_pciif_ad_out),
    .wbu_pciif_ad_en_out           (wbu_pciif_ad_en_out),
    .wbu_pciif_cbe_out             (wbu_pciif_cbe_out),
    .wbu_pciif_cbe_en_out          (wbu_pciif_cbe_en_out),
    .wbu_err_addr_out              (wbu_err_addr_out),
    .wbu_err_bc_out                (wbu_err_bc_out),
    .wbu_err_signal_out            (wbu_err_signal_out),
    .wbu_err_source_out            (wbu_err_source_out),
    .wbu_err_rty_exp_out           (wbu_err_rty_exp_out),
    .wbu_tabort_rec_out            (wbu_tabort_rec_out),
    .wbu_mabort_rec_out            (wbu_mabort_rec_out),
    .wbu_conf_offset_out           (wbu_conf_offset_out),
    .wbu_conf_renable_out          (wbu_conf_renable_out),
    .wbu_conf_wenable_out          (wbu_conf_wenable_out),
    .wbu_conf_be_out               (wbu_conf_be_out),
    .wbu_conf_data_out             (wbu_conf_data_out),
    .wbu_del_read_comp_pending_out (wbu_del_read_comp_pending_out),
    .wbu_wbw_fifo_empty_out        (wbu_wbw_fifo_empty_out),
    .wbu_latency_tim_val_in        (wbu_latency_tim_val_in),
    .wbu_ad_load_out               (wbu_ad_load_out),
    .wbu_ad_load_on_transfer_out   (wbu_ad_load_on_transfer_out),
    .wbu_pciif_trdy_reg_in         (wbu_pciif_trdy_reg_in),
    .wbu_pciif_stop_reg_in         (wbu_pciif_stop_reg_in),
    .wbu_pciif_devsel_reg_in       (wbu_pciif_devsel_reg_in)

`ifdef PCI_BIST
    ,
    .mbist_si_i       (mbist_si_i),
    .mbist_so_o       (mbist_so_o_internal),
    .mbist_ctrl_i       (mbist_ctrl_i)
`endif
);

// PCI TARGET UNIT INPUTS
wire    [31:0]  pciu_mdata_in                   =   wbm_dat_i ;
wire            pciu_ack_in                     =   wbm_ack_i ;
wire            pciu_rty_in                     =   wbm_rty_i ;
wire            pciu_err_in                     =   wbm_err_i ;

wire    [5:0]   pciu_map_in                     =   {
                                                     conf_pci_mem_io5_out,
                                                     conf_pci_mem_io4_out,
                                                     conf_pci_mem_io3_out,
                                                     conf_pci_mem_io2_out,
                                                     conf_pci_mem_io1_out,
                                                     conf_pci_mem_io0_out
                                                    } ;

wire    [5:0]   pciu_pref_en_in                 =   {
                                                     conf_pci_img_ctrl5_out[0],
                                                     conf_pci_img_ctrl4_out[0],
                                                     conf_pci_img_ctrl3_out[0],
                                                     conf_pci_img_ctrl2_out[0],
                                                     conf_pci_img_ctrl1_out[0],
                                                     conf_pci_img_ctrl0_out[0]
                                                    };

wire    [5:0]   pciu_at_en_in                   =   {
                                                     conf_pci_img_ctrl5_out[1],
                                                     conf_pci_img_ctrl4_out[1],
                                                     conf_pci_img_ctrl3_out[1],
                                                     conf_pci_img_ctrl2_out[1],
                                                     conf_pci_img_ctrl1_out[1],
                                                     conf_pci_img_ctrl0_out[1]
                                                    } ;

wire            pciu_mem_enable_in              =   conf_mem_space_enable_out ;
wire            pciu_io_enable_in               =   conf_io_space_enable_out ;

wire            pciu_wbw_fifo_empty_in          =   wbu_wbw_fifo_empty_out ;
wire			pciu_wbu_del_read_comp_pending_in	=	wbu_del_read_comp_pending_out ;
wire            pciu_wbu_frame_en_in            =   out_bckp_frame_en_out ;

`ifdef HOST
    wire    [31:0]  pciu_conf_data_in           =   conf_r_data_out ;
`else
`ifdef GUEST
    wire    [31:0]  pciu_conf_data_in           =   conf_w_data_out ;
`endif
`endif

wire    [pci_ba0_width   - 1:0] pciu_bar0_in =   conf_pci_ba0_out    ;
wire    [pci_ba1_5_width - 1:0] pciu_bar1_in =   conf_pci_ba1_out ;
wire    [pci_ba1_5_width - 1:0] pciu_bar2_in =   conf_pci_ba2_out ;
wire    [pci_ba1_5_width - 1:0] pciu_bar3_in =   conf_pci_ba3_out ;
wire    [pci_ba1_5_width - 1:0] pciu_bar4_in =   conf_pci_ba4_out ;
wire    [pci_ba1_5_width - 1:0] pciu_bar5_in =   conf_pci_ba5_out ;
wire    [pci_ba1_5_width - 1:0] pciu_am0_in  =   conf_pci_am0_out ;
wire    [pci_ba1_5_width - 1:0] pciu_am1_in  =   conf_pci_am1_out ;
wire    [pci_ba1_5_width - 1:0] pciu_am2_in  =   conf_pci_am2_out ;
wire    [pci_ba1_5_width - 1:0] pciu_am3_in  =   conf_pci_am3_out ;
wire    [pci_ba1_5_width - 1:0] pciu_am4_in  =   conf_pci_am4_out ;
wire    [pci_ba1_5_width - 1:0] pciu_am5_in  =   conf_pci_am5_out ;
wire    [pci_ba1_5_width - 1:0] pciu_ta0_in  =   conf_pci_ta0_out ;
wire    [pci_ba1_5_width - 1:0] pciu_ta1_in  =   conf_pci_ta1_out ;
wire    [pci_ba1_5_width - 1:0] pciu_ta2_in  =   conf_pci_ta2_out ;
wire    [pci_ba1_5_width - 1:0] pciu_ta3_in  =   conf_pci_ta3_out ;
wire    [pci_ba1_5_width - 1:0] pciu_ta4_in  =   conf_pci_ta4_out ;
wire    [pci_ba1_5_width - 1:0] pciu_ta5_in  =   conf_pci_ta5_out ;

wire    [7:0]   pciu_cache_line_size_in                 =   conf_cache_line_size_to_wb_out ;
wire            pciu_cache_lsize_not_zero_in            =   conf_cache_lsize_not_zero_to_wb_out ;

wire            pciu_pciif_frame_in                     =   int_pci_frame   ;
wire            pciu_pciif_irdy_in                      =   int_pci_irdy    ;
wire            pciu_pciif_idsel_in                     =   pci_idsel_i ;
wire            pciu_pciif_frame_reg_in                 =   in_reg_frame_out ;
wire            pciu_pciif_irdy_reg_in                  =   in_reg_irdy_out ;
wire            pciu_pciif_idsel_reg_in                 =   in_reg_idsel_out ;
wire    [31:0]  pciu_pciif_ad_reg_in                    =   in_reg_ad_out ;
wire    [3:0]   pciu_pciif_cbe_reg_in                   =   in_reg_cbe_out ;
wire    [3:0]   pciu_pciif_cbe_in                       =   int_pci_cbe ;

wire            pciu_pciif_bckp_trdy_en_in              =   out_bckp_trdy_en_out ;
wire            pciu_pciif_bckp_devsel_in               =   out_bckp_devsel_out ;
wire            pciu_pciif_bckp_trdy_in                 =   out_bckp_trdy_out ;
wire            pciu_pciif_bckp_stop_in                 =   out_bckp_stop_out ;
wire            pciu_pciif_trdy_reg_in                  =   in_reg_trdy_out ;
wire            pciu_pciif_stop_reg_in                  =   in_reg_stop_out ;

pci_target_unit pci_target_unit
(
    .reset_in                       (reset),
    .wb_clock_in                    (wb_clk),
    .pci_clock_in                   (pci_clk),
    .pciu_wbm_adr_o                 (pciu_adr_out),
    .pciu_wbm_dat_o                 (pciu_mdata_out),
    .pciu_wbm_dat_i                 (pciu_mdata_in),
    .pciu_wbm_cyc_o                 (pciu_cyc_out),
    .pciu_wbm_stb_o                 (pciu_stb_out),
    .pciu_wbm_we_o                  (pciu_we_out),
    .pciu_wbm_cti_o                 (pciu_cti_out),
    .pciu_wbm_bte_o                 (pciu_bte_out),
    .pciu_wbm_sel_o                 (pciu_sel_out),
    .pciu_wbm_ack_i                 (pciu_ack_in),
    .pciu_wbm_rty_i                 (pciu_rty_in),
    .pciu_wbm_err_i                 (pciu_err_in),
    .pciu_mem_enable_in             (pciu_mem_enable_in),
    .pciu_io_enable_in              (pciu_io_enable_in),
    .pciu_map_in                    (pciu_map_in),
    .pciu_pref_en_in                (pciu_pref_en_in),
    .pciu_conf_data_in              (pciu_conf_data_in),
    .pciu_wbw_fifo_empty_in         (pciu_wbw_fifo_empty_in),
    .pciu_wbu_del_read_comp_pending_in	(pciu_wbu_del_read_comp_pending_in),
    .pciu_wbu_frame_en_in           (pciu_wbu_frame_en_in),
    .pciu_bar0_in                   (pciu_bar0_in),
    .pciu_bar1_in                   (pciu_bar1_in),
    .pciu_bar2_in                   (pciu_bar2_in),