pci_wb_slave_unit.v

用verilog编写的pci——rtl级。

//////////////////////////////////////////////////////////////////////
////                                                              ////
////  File name "wb_slave_unit.v"                                 ////
////                                                              ////
////  This file is part of the "PCI bridge" project               ////
////  http://www.opencores.org/cores/pci/                         ////
////                                                              ////
////  Author(s):                                                  ////
////      - Miha Dolenc ([e-mail])                     ////
////                                                              ////
////  All additional information is avaliable in the README       ////
////  file.                                                       ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2001 Miha Dolenc, [e-mail]          ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: pci_wb_slave_unit.v,v $
// Revision 1.3  2004/01/24 11:54:18  mihad
// Update! SPOCI Implemented!
//
// Revision 1.2  2003/10/17 09:11:52  markom
// mbist signals updated according to newest convention
//
// Revision 1.1  2003/01/27 16:49:31  mihad
// Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed.
//
// Revision 1.8  2002/10/18 03:36:37  tadejm
// Changed wrong signal name mbist_sen into mbist_ctrl_i.
//
// Revision 1.7  2002/10/17 22:49:22  tadejm
// Changed BIST signals for RAMs.
//
// Revision 1.6  2002/10/11 10:09:01  mihad
// Added additional testcase and changed rst name in BIST to trst
//
// Revision 1.5  2002/10/08 17:17:06  mihad
// Added BIST signals for RAMs.
//
// Revision 1.4  2002/09/25 15:53:52  mihad
// Removed all logic from asynchronous reset network
//
// Revision 1.3  2002/02/01 15:25:13  mihad
// Repaired a few bugs, updated specification, added test bench files and design document
//
// Revision 1.2  2001/10/05 08:14:30  mihad
// Updated all files with inclusion of timescale file for simulation purposes.
//
// Revision 1.1.1.1  2001/10/02 15:33:46  mihad
// New project directory structure
//
//

// Module instantiates and connects other modules lower in hierarcy
// Wishbone slave unit consists of modules that together form datapath
// between external WISHBONE masters and external PCI targets
`include "pci_constants.v"

// synopsys translate_off
`include "timescale.v"
// synopsys translate_on

module pci_wb_slave_unit
(
    reset_in,
    wb_clock_in,
    pci_clock_in,
    ADDR_I,
    SDATA_I,
    SDATA_O,
    CYC_I,
    STB_I,
    WE_I,
    SEL_I,
    ACK_O,
    RTY_O,
    ERR_O,
    CAB_I,
    wbu_map_in,
    wbu_pref_en_in,
    wbu_mrl_en_in,
    wbu_pci_drcomp_pending_in,
    wbu_conf_data_in,
    wbu_pciw_empty_in,
    wbu_bar0_in,
    wbu_bar1_in,
    wbu_bar2_in,
    wbu_bar3_in,
    wbu_bar4_in,
    wbu_bar5_in,
    wbu_am0_in,
    wbu_am1_in,
    wbu_am2_in,
    wbu_am3_in,
    wbu_am4_in,
    wbu_am5_in,
    wbu_ta0_in,
    wbu_ta1_in,
    wbu_ta2_in,
    wbu_ta3_in,
    wbu_ta4_in,
    wbu_ta5_in,
    wbu_at_en_in,
    wbu_ccyc_addr_in ,
    wbu_master_enable_in,
    wb_init_complete_in,
    wbu_cache_line_size_not_zero,
    wbu_cache_line_size_in,
    wbu_pciif_gnt_in,
    wbu_pciif_frame_in,
    wbu_pciif_irdy_in,
    wbu_pciif_trdy_in,
    wbu_pciif_trdy_reg_in,
    wbu_pciif_stop_in,
    wbu_pciif_stop_reg_in,
    wbu_pciif_devsel_in,
    wbu_pciif_devsel_reg_in,
    wbu_pciif_ad_reg_in,
    wbu_pciif_req_out,
    wbu_pciif_frame_out,
    wbu_pciif_frame_en_out,
    wbu_pciif_frame_en_in,
    wbu_pciif_frame_out_in,
    wbu_pciif_frame_load_out,
    wbu_pciif_irdy_out,
    wbu_pciif_irdy_en_out,
    wbu_pciif_ad_out,
    wbu_pciif_ad_en_out,
    wbu_pciif_cbe_out,
    wbu_pciif_cbe_en_out,
    wbu_err_addr_out,
    wbu_err_bc_out,
    wbu_err_signal_out,
    wbu_err_source_out,
    wbu_err_rty_exp_out,
    wbu_tabort_rec_out,
    wbu_mabort_rec_out,
    wbu_conf_offset_out,
    wbu_conf_renable_out,
    wbu_conf_wenable_out,
    wbu_conf_be_out,
    wbu_conf_data_out,
    wbu_del_read_comp_pending_out,
    wbu_wbw_fifo_empty_out,
    wbu_latency_tim_val_in,
    wbu_ad_load_out,
    wbu_ad_load_on_transfer_out

`ifdef PCI_BIST
    ,
    // debug chain signals
    mbist_si_i,       // bist scan serial in
    mbist_so_o,       // bist scan serial out
    mbist_ctrl_i        // bist chain shift control
`endif
);

input reset_in,
      wb_clock_in,
      pci_clock_in ;

input   [31:0]  ADDR_I   ;
input   [31:0]  SDATA_I  ;
output  [31:0]  SDATA_O  ;
input           CYC_I    ;
input           STB_I    ;
input           WE_I     ;
input   [3:0]   SEL_I    ;
output          ACK_O    ;
output          RTY_O    ;
output          ERR_O    ;
input           CAB_I    ;

input   [5:0]   wbu_map_in ;
input   [5:0]   wbu_pref_en_in ;
input   [5:0]   wbu_mrl_en_in ;

input           wbu_pci_drcomp_pending_in ;

input   [31:0]  wbu_conf_data_in ;

input           wbu_pciw_empty_in ;

input   [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] wbu_bar0_in ;
input   [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] wbu_bar1_in ;
input   [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] wbu_bar2_in ;
input   [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] wbu_bar3_in ;
input   [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] wbu_bar4_in ;
input   [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] wbu_bar5_in ;
input   [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] wbu_am0_in ;
input   [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] wbu_am1_in ;
input   [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] wbu_am2_in ;
input   [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] wbu_am3_in ;
input   [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] wbu_am4_in ;
input   [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] wbu_am5_in ;
input   [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] wbu_ta0_in ;
input   [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] wbu_ta1_in ;
input   [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] wbu_ta2_in ;
input   [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] wbu_ta3_in ;
input   [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] wbu_ta4_in ;
input   [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] wbu_ta5_in ;
input   [5:0]                               wbu_at_en_in ;

input   [23:0]  wbu_ccyc_addr_in ;

input           wbu_master_enable_in    ;
input           wb_init_complete_in     ;

input			wbu_cache_line_size_not_zero ;
input   [7:0]   wbu_cache_line_size_in ;

input           wbu_pciif_gnt_in ;
input           wbu_pciif_frame_in ;
input           wbu_pciif_frame_en_in ;
input           wbu_pciif_irdy_in ;
input           wbu_pciif_trdy_in;
input           wbu_pciif_trdy_reg_in;
input           wbu_pciif_stop_in ;
input           wbu_pciif_stop_reg_in ;
input           wbu_pciif_devsel_in ;
input           wbu_pciif_devsel_reg_in ;
input [31:0]    wbu_pciif_ad_reg_in ;

output          wbu_pciif_req_out ;
output          wbu_pciif_frame_out ;
output          wbu_pciif_frame_en_out ;
input           wbu_pciif_frame_out_in ;
output          wbu_pciif_frame_load_out ;
output          wbu_pciif_irdy_out ;
output          wbu_pciif_irdy_en_out ;
output  [31:0]  wbu_pciif_ad_out ;
output          wbu_pciif_ad_en_out ;
output  [3:0]   wbu_pciif_cbe_out ;
output          wbu_pciif_cbe_en_out ;

output  [31:0]  wbu_err_addr_out ;
output  [3:0]   wbu_err_bc_out ;
output          wbu_err_signal_out ;
output          wbu_err_source_out ;
output          wbu_err_rty_exp_out ;
output          wbu_tabort_rec_out ;
output          wbu_mabort_rec_out ;

output  [11:0]  wbu_conf_offset_out ;
output          wbu_conf_renable_out ;
output          wbu_conf_wenable_out ;
output  [3:0]   wbu_conf_be_out ;
output  [31:0]  wbu_conf_data_out ;

output          wbu_del_read_comp_pending_out ;
output          wbu_wbw_fifo_empty_out ;

input   [7:0]   wbu_latency_tim_val_in ;

output          wbu_ad_load_out ;
output          wbu_ad_load_on_transfer_out ;

`ifdef PCI_BIST
/*-----------------------------------------------------
BIST debug chain port signals
-----------------------------------------------------*/
input   mbist_si_i;       // bist scan serial in
output  mbist_so_o;       // bist scan serial out
input [`PCI_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;       // bist chain shift control
`endif

// pci master interface outputs