spi_equal3_rtl.v

verilog语言写的SPI接口,全同步设计,低门数,可以很容易应用到嵌入设计方案中.

// HDLi Version 3.0 (beta)
// Parameters: compare -b 3 -eq     -S 0 -p 3   -l vsc983 -Synopsys -rtl -nentity -nadd_p -ntiming -verilog -br 0,4,8,12,32,0  
// spi_equal3: 9.00 physical gates (vsc983)
// spi_equal3: 233.37 squm area (vsc983)
// -----------------------------------------------------------------------------
//                            VLSI Technology, Inc.
// -----------------------------------------------------------------------------
// Copyright 1999 by VLSI Technology, Inc. All rights reserved.
// 
// This module is property of VLSI Technology, Inc (VLSI) and its use is
// granted to the customer for the sole purpose of implementing in silicon
// provided by VLSI. This module may only be used in accordance with the
// provisions of the Design Integrator License Agreement.
// 
// -----------------------------------------------------------------------------
//                        Comparator Compiler Version 1.0a
// -----------------------------------------------------------------------------
// spi_equal3 : RTL Verilog
// (RTL is optimized for simulation, not synthesis)
// "spi_equal3.v" contains the Structural Verilog
//
// Compiled by coste_e on Fri Jun 18 10:49:48 1999
// -----------------------------------------------------------------------------
module spi_equal3 (
                   a,
                   b,
                   aeqb);

   input  [2:0] a;
   input  [2:0] b;
   output       aeqb;

      assign  aeqb = (a == b); 

endmodule // spi_equal3

// -----------------------------------------------------------------------------
// Verilog Component Instantiation:
// -----------------------------------------------------------------------------
/*
   spi_equal3 u1 (.a(),        //  3 bit Source Operand
                  .b(),        //  3 bit Source Operand
                  .aeqb());    // A == B

*/
// -----------------------------------------------------------------------------
// Verilog Synthesis Commands:
// -----------------------------------------------------------------------------
/*
   set_dont_touch find(design, spi_equal3, -hierarchy)
   remove_attribute find(design, spi_equal3, -hierarchy) dont_touch
   set_ungroup find(design, spi_equal3, -hierarchy)
*/
// -----------------------------------------------------------------------------