spi_cs_cnt.v

verilog语言写的SPI接口,全同步设计,低门数,可以很容易应用到嵌入设计方案中.

// HDLi Version 3.0c IP Bundle 1999.07.23
// Parameters: counter -b3 -t0 -p0 -f1 -L1 -C  -R  -N -M  -r 0x3 -n 0x7  -l vsc983 -padlib vst8p31 -Synopsys -rtl -nentity -nadd_p -ntiming -verilog -br 0,4,8,12,32,0  
// spi_cs_cnt: 33.67 physical gates (vsc983)
// spi_cs_cnt: 872.98 squm area (vsc983)
// -----------------------------------------------------------------------------
//                            VLSI Technology, Inc.
// -----------------------------------------------------------------------------
// Copyright 1999 by VLSI Technology, Inc. All rights reserved.
// 
// This module is property of VLSI Technology, Inc (VLSI) and its use is
// granted to the customer for the sole purpose of implementing in silicon
// provided by VLSI. This module may only be used in accordance with the
// provisions of the Design Integrator License Agreement.
// 
// -----------------------------------------------------------------------------
//                          Counter Compiler Version 1.1b
// -----------------------------------------------------------------------------
// spi_cs_cnt : structural Verilog
// "spi_cs_cnt_rtl.v" contains the RTL Verilog
//
// Compiled by coste on Wed Sep  8 13:58:36 1999
// -----------------------------------------------------------------------------

module spi_cs_cnt (
                   clk,
                   cdn,
                   load,
                   datain,
                   q,
                   tci);

   input        clk;
   input        cdn;
   input        load;
   input  [2:0] datain;
   output [2:0] q;
   output       tci;

   supply1 vdd;
   supply0 vss;


   wire   n000001;
   assign n000001 = clk;
   wire   n000002;
   assign n000002 = cdn;
   wire   n000003;
   assign n000003 = load;
   wire   n000006;
   assign n000006 = datain[2];
   wire   n000005;
   assign n000005 = datain[1];
   wire   n000004;
   assign n000004 = datain[0];
   wire   n000009;
   assign q[2] = n000009;
   wire   n000008;
   assign q[1] = n000008;
   wire   n000007;
   assign q[0] = n000007;
   wire   n000010;
   assign tci = n000010;

   in01d1  u000001(
                   .i(n000007),
                   .zn(n000012));
   in01d1  u000002(
                   .i(n000003),
                   .zn(n000021));
   mfctnq1  u000003_reg(
                        .da(n000014),
                        .db(n000006),
                        .sa(n000021),
                        .cp(n000001),
                        .cdn(n000002),
                        .q(n000009));
   mfptnq1  u000004_reg(
                        .da(n000013),
                        .db(n000005),
                        .sa(n000021),
                        .cp(n000001),
                        .sdn(n000002),
                        .q(n000008));
   mfptnq1  u000005_reg(
                        .da(n000012),
                        .db(n000004),
                        .sa(n000021),
                        .cp(n000001),
                        .sdn(n000002),
                        .q(n000007));
   nr03d1  u000006(
                   .a1(n000009),
                   .a2(n000008),
                   .a3(n000007),
                   .zn(n000010));
   or02d1  u000007(
                   .a1(n000007),
                   .a2(n000008),
                   .z(n000024));
   xn02d1  u000008(
                   .a1(n000009),
                   .a2(n000024),
                   .zn(n000014));
   xn02d1  u000009(
                   .a1(n000008),
                   .a2(n000007),
                   .zn(n000013));

endmodule // spi_cs_cnt

// -----------------------------------------------------------------------------
// Verilog Component Instantiation:
// -----------------------------------------------------------------------------
/*
   spi_cs_cnt u1 (.clk(),       // Clock Input
                  .cdn(),       // Clear Direct Not Input
                  .load(),      // Load Control Input
                  .datain(),    // Data Input
                  .q(),         //  3 bit Result
                  .tci());      // Terminal Count Indicator

*/
// -----------------------------------------------------------------------------
// Verilog Synthesis Commands:
// -----------------------------------------------------------------------------
/*
   set_dont_touch find(design, spi_cs_cnt, -hierarchy)
   remove_attribute find(design, spi_cs_cnt, -hierarchy) dont_touch
   set_ungroup find(design, spi_cs_cnt, -hierarchy)
*/
// -----------------------------------------------------------------------------