spi_bitcounter.v

verilog语言写的SPI接口,全同步设计,低门数,可以很容易应用到嵌入设计方案中.

// HDLi Version 3.0d IP Bundle 1999.08.25
// Parameters: counter -b6 -t0 -p1 -f0 -L0 -C -c -R -S  -M   -l vsc983 -padlib vst8p31 -Synopsys -rtl -nentity -nadd_p -ntiming -nls -verilog -br 0,4,8,12,32,0  
// spi_bitcounter: 95.33 physical gates (vsc983)
// spi_bitcounter: 2471.99 squm area (vsc983)
// -----------------------------------------------------------------------------
//                            VLSI Technology, Inc.
// -----------------------------------------------------------------------------
// Copyright 1999 by VLSI Technology, Inc. All rights reserved.
// 
// This module is property of VLSI Technology, Inc (VLSI) and its use is
// granted to the customer for the sole purpose of implementing in silicon
// provided by VLSI. This module may only be used in accordance with the
// provisions of the Design Integrator License Agreement.
// 
// -----------------------------------------------------------------------------
//                          Counter Compiler Version 1.1b
// -----------------------------------------------------------------------------
// spi_bitcounter : structural Verilog
// "spi_bitcounter_rtl.v" contains the RTL Verilog
//
// Compiled by coste on Wed Oct 27 15:09:44 1999
// -----------------------------------------------------------------------------

module spi_bitcounter (
                       clk,
                       cdn,
                       csn,
                       cen,
                       maxval,
                       q,
                       tci);

   input        clk;
   input        cdn;
   input        csn;
   input        cen;
   input  [5:0] maxval;
   output [5:0] q;
   output       tci;

   supply1 vdd;
   supply0 vss;


   wire   n000001;
   assign n000001 = clk;
   wire   n000002;
   assign n000002 = cdn;
   wire   n000003;
   assign n000003 = csn;
   wire   n000004;
   assign n000004 = cen;
   wire   n000010;
   assign n000010 = maxval[5];
   wire   n000009;
   assign n000009 = maxval[4];
   wire   n000008;
   assign n000008 = maxval[3];
   wire   n000007;
   assign n000007 = maxval[2];
   wire   n000006;
   assign n000006 = maxval[1];
   wire   n000005;
   assign n000005 = maxval[0];
   wire   n000016;
   assign q[5] = n000016;
   wire   n000015;
   assign q[4] = n000015;
   wire   n000014;
   assign q[3] = n000014;
   wire   n000013;
   assign q[2] = n000013;
   wire   n000012;
   assign q[1] = n000012;
   wire   n000011;
   assign q[0] = n000011;
   wire   n000017;
   assign tci = n000017;

   an02d1  u000001(
                   .a1(n000048),
                   .a2(n000004),
                   .z(n000053));
   an03d1  u000002(
                   .a1(n000070),
                   .a2(n000028),
                   .a3(n000027),
                   .z(n000040));
   an03d1  u000003(
                   .a1(n000070),
                   .a2(n000030),
                   .a3(n000027),
                   .z(n000041));
   an03d1  u000004(
                   .a1(n000070),
                   .a2(n000032),
                   .a3(n000027),
                   .z(n000042));
   an03d1  u000005(
                   .a1(n000070),
                   .a2(n000034),
                   .a3(n000027),
                   .z(n000043));
   an03d1  u000006(
                   .a1(n000070),
                   .a2(n000036),
                   .a3(n000027),
                   .z(n000044));
   an03d1  u000007(
                   .a1(n000070),
                   .a2(n000038),
                   .a3(n000027),
                   .z(n000045));
   an04d1  u000008(
                   .a1(n000014),
                   .a2(n000012),
                   .a3(n000011),
                   .a4(n000013),
                   .z(n000048));
   dfctnq1  u000009_reg(
                        .d(n000045),
                        .cp(n000001),
                        .cdn(n000071),
                        .q(n000016));
   dfctnq1  u000010_reg(
                        .d(n000044),
                        .cp(n000001),
                        .cdn(n000071),
                        .q(n000015));
   dfctnq1  u000011_reg(
                        .d(n000043),
                        .cp(n000001),
                        .cdn(n000071),
                        .q(n000014));
   dfctnq1  u000012_reg(
                        .d(n000042),
                        .cp(n000001),
                        .cdn(n000071),
                        .q(n000013));
   dfctnq2  u000013_reg(
                        .d(n000041),
                        .cp(n000001),
                        .cdn(n000071),
                        .q(n000012));
   dfctnq2  u000014_reg(
                        .d(n000040),
                        .cp(n000001),
                        .cdn(n000071),
                        .q(n000011));
   fn01d1  u000015(
                   .a1(n000016),
                   .b1(n000010),
                   .zn(n000023));
   fn01d1  u000016(
                   .a1(n000015),
                   .b1(n000009),
                   .zn(n000022));
   fn01d1  u000017(
                   .a1(n000014),
                   .b1(n000008),
                   .zn(n000021));
   fn01d1  u000018(
                   .a1(n000013),
                   .b1(n000007),
                   .zn(n000020));
   fn01d1  u000019(
                   .a1(n000012),
                   .b1(n000006),
                   .zn(n000019));
   fn01d1  u000020(
                   .a1(n000011),
                   .b1(n000005),
                   .zn(n000018));
   nd02d1  u000021(
                   .a1(n000053),
                   .a2(n000015),
                   .zn(n000051));
   nd02d1  u000022(
                   .a1(n000050),
                   .a2(n000011),
                   .zn(n000059));
   nd02d2  u000023(
                   .a1(n000017),
                   .a2(n000004),
                   .zn(n000027));
   nd02d1  u000024(
                   .a1(n000019),
                   .a2(n000018),
                   .zn(n000025));
   nd03d1  u000025(
                   .a1(n000050),
                   .a2(n000012),
                   .a3(n000011),
                   .zn(n000057));
   nd04d1  u000026(
                   .a1(n000050),
                   .a3(n000012),
                   .a4(n000011),
                   .a2(n000013),
                   .zn(n000055));
   nd04d1  u000027(
                   .a1(n000023),
                   .a3(n000021),
                   .a4(n000020),
                   .a2(n000022),
                   .zn(n000024));
   ni01d2  u000028(
                   .i(n000002),
                   .z(n000071));
   ni01d2  u000029(
                   .i(n000003),
                   .z(n000070));
   ni01d1  u000030(
                   .i(n000004),
                   .z(n000050));
   nr02d1  u000031(
                   .a1(n000025),
                   .a2(n000024),
                   .zn(n000017));
   xn02d1  u000032(
                   .a1(n000051),
                   .a2(n000016),
                   .zn(n000038));
   xn02d1  u000033(
                   .a1(n000055),
                   .a2(n000014),
                   .zn(n000034));
   xn02d1  u000034(
                   .a1(n000057),
                   .a2(n000013),
                   .zn(n000032));
   xn02d1  u000035(
                   .a1(n000059),
                   .a2(n000012),
                   .zn(n000030));
   xo02d1  u000036(
                   .a1(n000053),
                   .a2(n000015),
                   .z(n000036));
   xo02d1  u000037(
                   .a1(n000004),
                   .a2(n000011),
                   .z(n000028));

endmodule // spi_bitcounter

// -----------------------------------------------------------------------------
// Verilog Component Instantiation:
// -----------------------------------------------------------------------------
/*
   spi_bitcounter u1 (.clk(),       // Clock Input
                      .cdn(),       // Clear Direct Not Input
                      .csn(),       // Clear Synchronous Not Input
                      .cen(),       // Count Enable Input
                      .maxval(),    // Programmable Maximum Count Value
                      .q(),         //  6 bit Result
                      .tci());      // Terminal Count Indicator

*/
// -----------------------------------------------------------------------------
// Verilog Synthesis Commands:
// -----------------------------------------------------------------------------
/*
   set_dont_touch find(design, spi_bitcounter, -hierarchy)
   remove_attribute find(design, spi_bitcounter, -hierarchy) dont_touch
   set_ungroup find(design, spi_bitcounter, -hierarchy)
*/
// -----------------------------------------------------------------------------