spi_comp3_ge_rtl.v

verilog语言写的SPI接口,全同步设计,低门数,可以很容易应用到嵌入设计方案中.

// HDLi Version 3.0a (beta) IP Bundle 1999.02.18
// Parameters: compare -b 4   -ge   -S 0 -p 0   -l vsc983 -Synopsys -rtl -nentity -nadd_p -ntiming -verilog -br 0,4,8,12,32,0  
// spi_comp3_ge: 13.67 physical gates (vsc983)
// spi_comp3_ge: 354.38 squm area (vsc983)
// -----------------------------------------------------------------------------
//                            VLSI Technology, Inc.
// -----------------------------------------------------------------------------
// Copyright 1999 by VLSI Technology, Inc. All rights reserved.
// 
// This module is property of VLSI Technology, Inc (VLSI) and its use is
// granted to the customer for the sole purpose of implementing in silicon
// provided by VLSI. This module may only be used in accordance with the
// provisions of the Design Integrator License Agreement.
// 
// -----------------------------------------------------------------------------
//                        Comparator Compiler Version 1.0a
// -----------------------------------------------------------------------------
// spi_comp3_ge : RTL Verilog
// (RTL is optimized for simulation, not synthesis)
// "spi_comp3_ge.v" contains the Structural Verilog
//
// Compiled by coste on Tue Jul 27 15:11:48 1999
// -----------------------------------------------------------------------------
module spi_comp3_ge (
                     a,
                     b,
                     ageb);

   input  [3:0] a;
   input  [3:0] b;
   output       ageb;

      assign  ageb = (a >= b) ; 

endmodule // spi_comp3_ge

// -----------------------------------------------------------------------------
// Verilog Component Instantiation:
// -----------------------------------------------------------------------------
/*
   spi_comp3_ge u1 (.a(),        //  4 bit Source Operand
                    .b(),        //  4 bit Source Operand
                    .ageb());    // A >= B

*/
// -----------------------------------------------------------------------------
// Verilog Synthesis Commands:
// -----------------------------------------------------------------------------
/*
   set_dont_touch find(design, spi_comp3_ge, -hierarchy)
   remove_attribute find(design, spi_comp3_ge, -hierarchy) dont_touch
   set_ungroup find(design, spi_comp3_ge, -hierarchy)
*/
// -----------------------------------------------------------------------------