spi_clkdiv_count.v

verilog语言写的SPI接口,全同步设计,低门数,可以很容易应用到嵌入设计方案中.

// HDLi Version 3.0d IP Bundle 1999.08.25
// Parameters: counter -b4 -t0 -p1 -f0 -L0 -C  -R   -M   -l vsc983 -padlib vst8p31 -Synopsys -rtl -nentity -nadd_p -ntiming -verilog -br 0,4,8,12,32,0  
// spi_clkdiv_count: 51.00 physical gates (vsc983)
// spi_clkdiv_count: 1322.43 squm area (vsc983)
// -----------------------------------------------------------------------------
//                            VLSI Technology, Inc.
// -----------------------------------------------------------------------------
// Copyright 1999 by VLSI Technology, Inc. All rights reserved.
// 
// This module is property of VLSI Technology, Inc (VLSI) and its use is
// granted to the customer for the sole purpose of implementing in silicon
// provided by VLSI. This module may only be used in accordance with the
// provisions of the Design Integrator License Agreement.
// 
// -----------------------------------------------------------------------------
//                          Counter Compiler Version 1.1b
// -----------------------------------------------------------------------------
// spi_clkdiv_count : structural Verilog
// "spi_clkdiv_count_rtl.v" contains the RTL Verilog
//
// Compiled by coste on Wed Oct 27 16:04:09 1999
// -----------------------------------------------------------------------------

module spi_clkdiv_count (
                         clk,
                         cdn,
                         maxval,
                         q,
                         tci);

   input        clk;
   input        cdn;
   input  [3:0] maxval;
   output [3:0] q;
   output       tci;

   supply1 vdd;
   supply0 vss;


   wire   n000001;
   assign n000001 = clk;
   wire   n000002;
   assign n000002 = cdn;
   wire   n000006;
   assign n000006 = maxval[3];
   wire   n000005;
   assign n000005 = maxval[2];
   wire   n000004;
   assign n000004 = maxval[1];
   wire   n000003;
   assign n000003 = maxval[0];
   wire   n000010;
   assign q[3] = n000010;
   wire   n000009;
   assign q[2] = n000009;
   wire   n000008;
   assign q[1] = n000008;
   wire   n000007;
   assign q[0] = n000007;
   wire   n000011;
   assign tci = n000011;

   an02d1  u000001(
                   .a1(n000024),
                   .a2(n000017),
                   .z(n000025));
   an02d1  u000002(
                   .a1(n000022),
                   .a2(n000017),
                   .z(n000023));
   an02d1  u000003(
                   .a1(n000020),
                   .a2(n000017),
                   .z(n000021));
   an04d1  u000004(
                   .a1(n000015),
                   .a2(n000014),
                   .a3(n000013),
                   .a4(n000012),
                   .z(n000011));
   dfctnq1  u000005_reg(
                        .d(n000025),
                        .cp(n000001),
                        .cdn(n000002),
                        .q(n000010));
   dfctnq1  u000006_reg(
                        .d(n000023),
                        .cp(n000001),
                        .cdn(n000002),
                        .q(n000009));
   dfctnq1  u000007_reg(
                        .d(n000021),
                        .cp(n000001),
                        .cdn(n000002),
                        .q(n000008));
   dfctnq2  u000008_reg(
                        .d(n000019),
                        .cp(n000001),
                        .cdn(n000002),
                        .q(n000007));
   fn01d1  u000009(
                   .a1(n000010),
                   .b1(n000006),
                   .zn(n000015));
   fn01d1  u000010(
                   .a1(n000009),
                   .b1(n000005),
                   .zn(n000014));
   fn01d1  u000011(
                   .a1(n000008),
                   .b1(n000004),
                   .zn(n000013));
   fn01d1  u000012(
                   .a1(n000007),
                   .b1(n000003),
                   .zn(n000012));
   fn05d1  u000013(
                   .a1(n000017),
                   .b1(n000007),
                   .zn(n000019));
   in01d1  u000014(
                   .i(n000011),
                   .zn(n000017));
   nd02d1  u000015(
                   .a1(n000007),
                   .a2(n000008),
                   .zn(n000033));
   nd03d1  u000016(
                   .a1(n000007),
                   .a2(n000008),
                   .a3(n000009),
                   .zn(n000031));
   xn02d1  u000017(
                   .a1(n000031),
                   .a2(n000010),
                   .zn(n000024));
   xn02d1  u000018(
                   .a1(n000033),
                   .a2(n000009),
                   .zn(n000022));
   xo02d1  u000019(
                   .a1(n000007),
                   .a2(n000008),
                   .z(n000020));

endmodule // spi_clkdiv_count

// -----------------------------------------------------------------------------
// Verilog Component Instantiation:
// -----------------------------------------------------------------------------
/*
   spi_clkdiv_count u1 (.clk(),       // Clock Input
                        .cdn(),       // Clear Direct Not Input
                        .maxval(),    // Programmable Maximum Count Value
                        .q(),         //  4 bit Result
                        .tci());      // Terminal Count Indicator

*/
// -----------------------------------------------------------------------------
// Verilog Synthesis Commands:
// -----------------------------------------------------------------------------
/*
   set_dont_touch find(design, spi_clkdiv_count, -hierarchy)
   remove_attribute find(design, spi_clkdiv_count, -hierarchy) dont_touch
   set_ungroup find(design, spi_clkdiv_count, -hierarchy)
*/
// -----------------------------------------------------------------------------