spi_it.v

verilog语言写的SPI接口,全同步设计,低门数,可以很容易应用到嵌入设计方案中.

//----------------------------------------------------------------------------
// Project  : SCP1 - Standard Communication Platform Version 1
//----------------------------------------------------------------------------
// Source   : $Source: /db1/Razor_db/RAZOR_UNIVERSE/DOMAIN_01/SCP/Archive/RZ_VCS/scp1/design/arm_periph/spi/rtl/spi_it.v,v $
// Revision : $Revision: 1.3 $
// Date     : $Date: 1999/09/08 06:59:15 $
// Author   : $Author: coste_e $
//
//-Description----------------------------------------------------------------
// 
// 
// 
//---------------------------------------------------------------------------

module spi_it(
	      clk,
	      nreset,
	      read,
	      end_com,
	      fifo_level,
	      rx_trigger_level,
	      tx_trigger_level,
	      operation,
	      mask,
	      dma_mask,
	      start_from_reg,
	      busy,
	      n_opcode_addr_busy,
	      
	      spi_int,
	      it_val,
	      dma_req,
	      start_to_core,
	      dma_op_add_req);
   

   input clk;
   input nreset;
   input read;
   input end_com;
   input [3:0] fifo_level;
   input [3:0] rx_trigger_level;
   input [3:0] tx_trigger_level;
   input [2:0] operation;
   input [1:0] mask;
   input [1:0] dma_mask;
   input       start_from_reg;
   input       busy;
   input       n_opcode_addr_busy;
   
   output      spi_int;
   output [1:0] it_val;
   output 	dma_req;
   output 	start_to_core;
   output 	dma_op_add_req;
   
   wire [1:0] 	it_val;
   wire 	spi_int;
   wire 	dma_req;
   wire 	nbusy;
   wire 	dma_op_add_req;
    
   reg 		end_com_r; 
   reg 		end_com_it;		
   reg 		write_op_c;
   wire 	trigger_c;
   reg 		start_to_core;


   assign nbusy=~busy;
   assign dma_op_add_req=n_opcode_addr_busy&(~dma_mask[1]);
   
   //start generation

   always @(posedge clk or negedge nreset)
     begin
       if(!nreset)
	 start_to_core <= 1'b0;
       else
	 casex({start_to_core,start_from_reg,nbusy})
	  3'b00? : start_to_core <= 1'b0;
	  3'b010 : start_to_core <= 1'b0;
	  
	  3'b011 : start_to_core <= 1'b1;
	  3'b101 : start_to_core <= 1'b1;
	  
	  3'b1?0 : start_to_core <= 1'b0;
	  3'b111 : start_to_core <= 1'bx;
	  default :start_to_core <= 1'bx;
	 endcase // casex({start_to_core,start_from_reg,end_com})
     end // always @ (posedge clk or negedge nreset)
   
       
   
   //trigger interrupt generation
   
   spi_comp3_ge ge (.a({1'b0,tx_trigger_level[2:0]}),        //  4 bit Source Operand
		    .b(fifo_level),        //  4 bit Source Operand
		    .ageb(tx_trigger));    // A >= B
   

   
   spi_comp3_se se (.a({1'b0,rx_trigger_level[2:0]}),        //  4 bit Source Operand
		    .b(fifo_level),        //  4 bit Source Operand
                    .aleb(rx_trigger));    // A <= B

   
   assign trigger_c = write_op_c ? tx_trigger :rx_trigger;

   always @(operation)
    begin
      casex (operation)       
       3'b001  : write_op_c=1'b1;
       3'b010  : write_op_c=1'bx;
       3'b100  : write_op_c=1'b1;
       3'b110  : write_op_c=1'b1;
       default : write_op_c=1'b0;
      endcase // casex(operation)
    end // always @ (operation)

   
   
//endcom interrupt generation 
   always @(negedge nreset or posedge clk)
     if(!nreset)
       end_com_r<=1;
     else
       end_com_r<=~end_com;
   always @(negedge nreset or posedge clk)
     if (!nreset)
       	 end_com_it<=0;
     else
       begin
	 casex ({end_com_r,read,end_com,end_com_it})
	  4'b01xx : end_com_it<=0;
	  4'b00xx : end_com_it<=end_com_it;
	  4'b100x : end_com_it<=end_com_it;
	  4'b101x : end_com_it<=1;
	  4'b110x : end_com_it<=0;
	  4'b1110 : end_com_it<=1;
	  4'b1111 : end_com_it<=0;
	  default : end_com_it<=1'bx;
	 endcase // casex({end_com_r,read,end_com,end_com_it})
	 
       end // else: !if(!nreset)
   
   assign it_val[0]=(trigger_c&(~mask[0]));
   assign it_val[1]=(end_com_it&(~mask[1]));

   assign spi_int=it_val[0] | it_val[1];
					      
		  

   assign dma_req = trigger_c&(~dma_mask[0]);
   
   
   
endmodule // spi_it