spi_cs_cnt_rtl.v

verilog语言写的SPI接口,全同步设计,低门数,可以很容易应用到嵌入设计方案中.

// HDLi Version 3.0c IP Bundle 1999.07.23
// Parameters: counter -b3 -t0 -p0 -f1 -L1 -C  -R  -N -M  -r 0x3 -n 0x7  -l vsc983 -padlib vst8p31 -Synopsys -rtl -nentity -nadd_p -ntiming -verilog -br 0,4,8,12,32,0  
// spi_cs_cnt: 33.67 physical gates (vsc983)
// spi_cs_cnt: 872.98 squm area (vsc983)
// -----------------------------------------------------------------------------
//                            VLSI Technology, Inc.
// -----------------------------------------------------------------------------
// Copyright 1999 by VLSI Technology, Inc. All rights reserved.
// 
// This module is property of VLSI Technology, Inc (VLSI) and its use is
// granted to the customer for the sole purpose of implementing in silicon
// provided by VLSI. This module may only be used in accordance with the
// provisions of the Design Integrator License Agreement.
// 
// -----------------------------------------------------------------------------
//                          Counter Compiler Version 1.1b
// -----------------------------------------------------------------------------
// spi_cs_cnt : RTL Verilog
// (RTL is optimized for simulation, not synthesis)
// "spi_cs_cnt.v" contains the Structural Verilog
//
// Compiled by coste on Wed Sep  8 13:58:36 1999
// -----------------------------------------------------------------------------
module spi_cs_cnt (
                   clk,
                   cdn,
                   load,
                   datain,
                   q,
                   tci);

   input        clk;
   input        cdn;
   input        load;
   input  [2:0] datain;
   output [2:0] q;
   output       tci;


   parameter areset_value = 3'b011;
   parameter maxval = 3'b111;
   parameter minval = 3'b000;

   reg [2:0] q;
   wire tci;

   always @(posedge clk or negedge cdn)
   begin
      if (~cdn)
         q <= areset_value;
      else if (load)
         q <= datain;
      else
         q <= ((q <= minval || q >= maxval) && &(~q | minval)) ? maxval : (q-1);
   end

   assign tci = (q === minval);

endmodule // spi_cs_cnt

// -----------------------------------------------------------------------------
// Verilog Component Instantiation:
// -----------------------------------------------------------------------------
/*
   spi_cs_cnt u1 (.clk(),       // Clock Input
                  .cdn(),       // Clear Direct Not Input
                  .load(),      // Load Control Input
                  .datain(),    // Data Input
                  .q(),         //  3 bit Result
                  .tci());      // Terminal Count Indicator

*/
// -----------------------------------------------------------------------------
// Verilog Synthesis Commands:
// -----------------------------------------------------------------------------
/*
   set_dont_touch find(design, spi_cs_cnt, -hierarchy)
   remove_attribute find(design, spi_cs_cnt, -hierarchy) dont_touch
   set_ungroup find(design, spi_cs_cnt, -hierarchy)
*/
// -----------------------------------------------------------------------------