spi_page_cnt.v

verilog语言写的SPI接口,全同步设计,低门数,可以很容易应用到嵌入设计方案中.

// HDLi Version 3.0c IP Bundle 1999.07.23
// Parameters: counter -b8 -t0 -p0 -f1 -L1 -C -c -R  -N -M  -n 0xff  -l vsc983 -padlib vst8p31 -Synopsys -rtl -nentity -nadd_p -ntiming -verilog -br 0,4,8,12,32,0  
// spi_page_cnt: 100.33 physical gates (vsc983)
// spi_page_cnt: 2601.64 squm area (vsc983)
// -----------------------------------------------------------------------------
//                            VLSI Technology, Inc.
// -----------------------------------------------------------------------------
// Copyright 1999 by VLSI Technology, Inc. All rights reserved.
// 
// This module is property of VLSI Technology, Inc (VLSI) and its use is
// granted to the customer for the sole purpose of implementing in silicon
// provided by VLSI. This module may only be used in accordance with the
// provisions of the Design Integrator License Agreement.
// 
// -----------------------------------------------------------------------------
//                          Counter Compiler Version 1.1b
// -----------------------------------------------------------------------------
// spi_page_cnt : structural Verilog
// "spi_page_cnt_rtl.v" contains the RTL Verilog
//
// Compiled by coste on Tue Aug 24 15:34:44 1999
// -----------------------------------------------------------------------------

module spi_page_cnt (
                     clk,
                     cdn,
                     load,
                     datain,
                     cen,
                     q,
                     tci);

   input        clk;
   input        cdn;
   input        load;
   input  [7:0] datain;
   input        cen;
   output [7:0] q;
   output       tci;

   supply1 vdd;
   supply0 vss;


   wire   n000001;
   assign n000001 = clk;
   wire   n000002;
   assign n000002 = cdn;
   wire   n000003;
   assign n000003 = load;
   wire   n000011;
   assign n000011 = datain[7];
   wire   n000010;
   assign n000010 = datain[6];
   wire   n000009;
   assign n000009 = datain[5];
   wire   n000008;
   assign n000008 = datain[4];
   wire   n000007;
   assign n000007 = datain[3];
   wire   n000006;
   assign n000006 = datain[2];
   wire   n000005;
   assign n000005 = datain[1];
   wire   n000004;
   assign n000004 = datain[0];
   wire   n000012;
   assign n000012 = cen;
   wire   n000020;
   assign q[7] = n000020;
   wire   n000019;
   assign q[6] = n000019;
   wire   n000018;
   assign q[5] = n000018;
   wire   n000017;
   assign q[4] = n000017;
   wire   n000016;
   assign q[3] = n000016;
   wire   n000015;
   assign q[2] = n000015;
   wire   n000014;
   assign q[1] = n000014;
   wire   n000013;
   assign q[0] = n000013;
   wire   n000021;
   assign tci = n000021;

   an02d1  u000001(
                   .a1(n000023),
                   .a2(n000022),
                   .z(n000021));
   in01d1  u000002(
                   .i(n000012),
                   .zn(n000067));
   in01d2  u000003(
                   .i(n000003),
                   .zn(n000050));
   mfctnq1  u000004_reg(
                        .da(n000033),
                        .db(n000011),
                        .sa(n000050),
                        .cp(n000001),
                        .cdn(n000078),
                        .q(n000020));
   mfctnq1  u000005_reg(
                        .da(n000032),
                        .db(n000010),
                        .sa(n000050),
                        .cp(n000001),
                        .cdn(n000078),
                        .q(n000019));
   mfctnq1  u000006_reg(
                        .da(n000031),
                        .db(n000009),
                        .sa(n000050),
                        .cp(n000001),
                        .cdn(n000078),
                        .q(n000018));
   mfctnq1  u000007_reg(
                        .da(n000030),
                        .db(n000008),
                        .sa(n000050),
                        .cp(n000001),
                        .cdn(n000078),
                        .q(n000017));
   mfctnq1  u000008_reg(
                        .da(n000029),
                        .db(n000007),
                        .sa(n000050),
                        .cp(n000001),
                        .cdn(n000078),
                        .q(n000016));
   mfctnq1  u000009_reg(
                        .da(n000028),
                        .db(n000006),
                        .sa(n000050),
                        .cp(n000001),
                        .cdn(n000078),
                        .q(n000015));
   mfctnq1  u000010_reg(
                        .da(n000027),
                        .db(n000005),
                        .sa(n000050),
                        .cp(n000001),
                        .cdn(n000078),
                        .q(n000014));
   mfctnq1  u000011_reg(
                        .da(n000026),
                        .db(n000004),
                        .sa(n000050),
                        .cp(n000001),
                        .cdn(n000078),
                        .q(n000013));
   ni01d2  u000012(
                   .i(n000002),
                   .z(n000078));
   nr04d1  u000013(
                   .a1(n000016),
                   .a2(n000015),
                   .a3(n000014),
                   .a4(n000013),
                   .zn(n000023));
   nr04d1  u000014(
                   .a1(n000020),
                   .a2(n000019),
                   .a3(n000018),
                   .a4(n000017),
                   .zn(n000022));
   or02d1  u000015(
                   .a1(n000055),
                   .a2(n000019),
                   .z(n000053));
   or02d1  u000016(
                   .a1(n000057),
                   .a2(n000018),
                   .z(n000055));
   or02d1  u000017(
                   .a1(n000059),
                   .a2(n000017),
                   .z(n000057));
   or02d1  u000018(
                   .a1(n000061),
                   .a2(n000016),
                   .z(n000059));
   or02d1  u000019(
                   .a1(n000063),
                   .a2(n000015),
                   .z(n000061));
   or02d1  u000020(
                   .a1(n000065),
                   .a2(n000014),
                   .z(n000063));
   or02d1  u000021(
                   .a1(n000067),
                   .a2(n000013),
                   .z(n000065));
   xn02d1  u000022(
                   .a1(n000020),
                   .a2(n000053),
                   .zn(n000033));
   xn02d1  u000023(
                   .a1(n000019),
                   .a2(n000055),
                   .zn(n000032));
   xn02d1  u000024(
                   .a1(n000018),
                   .a2(n000057),
                   .zn(n000031));
   xn02d1  u000025(
                   .a1(n000017),
                   .a2(n000059),
                   .zn(n000030));
   xn02d1  u000026(
                   .a1(n000016),
                   .a2(n000061),
                   .zn(n000029));
   xn02d1  u000027(
                   .a1(n000015),
                   .a2(n000063),
                   .zn(n000028));
   xn02d1  u000028(
                   .a1(n000014),
                   .a2(n000065),
                   .zn(n000027));
   xn02d1  u000029(
                   .a1(n000013),
                   .a2(n000067),
                   .zn(n000026));

endmodule // spi_page_cnt

// -----------------------------------------------------------------------------
// Verilog Component Instantiation:
// -----------------------------------------------------------------------------
/*
   spi_page_cnt u1 (.clk(),       // Clock Input
                    .cdn(),       // Clear Direct Not Input
                    .load(),      // Load Control Input
                    .datain(),    // Data Input
                    .cen(),       // Count Enable Input
                    .q(),         //  8 bit Result
                    .tci());      // Terminal Count Indicator

*/
// -----------------------------------------------------------------------------
// Verilog Synthesis Commands:
// -----------------------------------------------------------------------------
/*
   set_dont_touch find(design, spi_page_cnt, -hierarchy)
   remove_attribute find(design, spi_page_cnt, -hierarchy) dont_touch
   set_ungroup find(design, spi_page_cnt, -hierarchy)
*/
// -----------------------------------------------------------------------------