spi_fifo.v

verilog语言写的SPI接口,全同步设计,低门数,可以很容易应用到嵌入设计方案中.

// HDLi Version 3.0 (beta)
// Parameters: sisfifo -d 8 -b 8 -retry 0 -t 1 -T 0 -D 1 -noreg -r 0 -flags 3
// -level 1 -period 50 -instname ''  -l vsc983 -Synopsys -rtl -nentity -nadd_p
// -ntiming -verilog -br 0,4,8,12,32,0  
// -----------------------------------------------------------------------------
//                            VLSI Technology, Inc.
// -----------------------------------------------------------------------------
// Copyright 1999 by VLSI Technology, Inc. All rights reserved.
// 
// This module is property of VLSI Technology, Inc (VLSI) and its use is
// granted to the customer for the sole purpose of implementing in silicon
// provided by VLSI. This module may only be used in accordance with the
// provisions of the Design Integrator License Agreement.
// 
// -----------------------------------------------------------------------------
//           Synchronous Interface FIFO - 1 Clock - Template Version 1.6
// -----------------------------------------------------------------------------
// spi_fifo.v : RTL Verilog
//
// Compiled by coste_e on Fri Jun 18 10:26:11 1999
// -----------------------------------------------------------------------------
// 
//    Option                                Value
//    ------                                -----
//    Word Depth:                           8
//    Word Width:                           8
//    Retry/Acknowledge Logic:              None
//    Memory Type:                          Flip/Flop
//    Output Register:                      No, Data valid before clock
//    Controller Reset Type:                Asynchronous
//    Provide Flush Input?                  No
//    Flags:                                Full
//                                          Empty
//    FIFO Depth Indicator Type:            Real Time Level
// 
// Functional Description:
//
// This HDL Template implements a FIFO function using either a latched
// memory, D Flip/Flop, RA5 RAM, or RS222 RAM. This is a synchronous
// design using one clock domain to facilitate scan insertion. The FIFO
// block references the following modules:
//
//   top level 
//
// -----------------------------------------------------------------------------
// Limitations:   None known at this time.
// -----------------------------------------------------------------------------
// Critical Timing:   Address hold time to RA5 or RS222 memory
// -----------------------------------------------------------------------------
// Non-Portable Instantiations: None
// -----------------------------------------------------------------------------
// Targeted Technologies: Any
// -----------------------------------------------------------------------------
// Author: Strategic Technology                      Creation Date: August, 1997
// -----------------------------------------------------------------------------
// Revision History:
// 1.0   8/96  Initial Release
// 1.1   8/97  Add RS222 / Retry support
// 1.3  11/97  Allow both a read and a write to both happen when full
// 1.4   4/98  Removed WEB from gating all FF in DFF version of FIFO
// 1.5   8/98  Updated scrits and added Latch/BIST support
// -----------------------------------------------------------------------------

`timescale 1ns/100ps

module spi_fifo (
                 cp,
                 nrd,
                 nwr,
                 nreseta,
                 di,
                 full,
                 empty,
                 level,
                 do);

   input        cp;  // FIFO clock
   input        nrd;  // FIFO Read enable
   input        nwr;  // FIFO Write enable
   input        nreseta;  // FIFO asynchronous reset
   input  [7:0] di;  // FIFO Data input
   output       full;  // FIFO Full flag
   output       empty;  // FIFO Empty flag
   output [3:0] level;  // FIFO Real time level indicator bus
   output [7:0] do;  // FIFO Data output bus


// DEFINE THE PHYSICAL PARAMETERS OF THE RAM

   parameter FIFO_DEPTH = 8,
             FIFO_WIDTH = 8,
             FIFO_ADDR_BITS  = 3,
             FIFO_LEVEL_BITS = 4;

   parameter tQ         = 1;  // clock to Q delay


// DEFINE INTERNAL VARIABLES
   wire web_int;                             // internal write signal 
   wire dfweb;                               // DFF version FIFO write signal
   wire we_int;                              // internal write signal 
   wire re_int;                              // internal read signal 
   wire srstb_int;                           // Synchronus reset signal
   reg fl,mt;                                // Internal empty and full flags
   reg [FIFO_LEVEL_BITS-1:0] lv;             // Internal real time level bus
   reg [FIFO_ADDR_BITS-1:0]  read_ptr;       // Read pointer
   reg [FIFO_ADDR_BITS-1:0]  write_ptr;      // Write pointer
   reg readl, writel;                        // Last operation saved states

   wire [FIFO_WIDTH-1:0]     ramout;         // Output RAM data        
   wire [FIFO_WIDTH-1:0]     dataout;        // Read data latch
   reg [FIFO_WIDTH-1:0]      ram_data[FIFO_DEPTH-1:0];  // RAM Data


// Assign outputs and interal signals
assign we_int = ~(nwr | (fl & nrd));
assign dfweb = (fl & nrd);
assign re_int = ~(nrd | mt);
assign web_int = ~we_int;

assign full = fl;
assign empty = mt;
assign level = lv;
assign do = dataout;
assign ramout = ram_data[read_ptr];

// -----------------------------------------------------------------------------
// Generate EMPTY and FULL flags
// -----------------------------------------------------------------------------
always @(readl or writel or read_ptr or write_ptr)
begin
  if ((readl == 1'b1) && (read_ptr == write_ptr))
    mt <= 1'b1;
  else
    mt <= 1'b0;

  if ((writel == 1'b1) && (read_ptr == write_ptr))
    fl <= 1'b1;
  else
    fl <= 1'b0;
end

// -----------------------------------------------------------------------------
// Generate Real Time LEVEL Bus
// -----------------------------------------------------------------------------
always @(fl or read_ptr or write_ptr)
begin
  if ((fl == 1'b0) && (write_ptr >= read_ptr))
    lv <= write_ptr - read_ptr;
  else
    lv <= write_ptr - read_ptr + FIFO_DEPTH;
end

// -----------------------------------------------------------------------------
// Read Address Counter
// -----------------------------------------------------------------------------
always @(posedge cp or negedge nreseta)
begin
  if (nreseta == 1'b0)
    read_ptr <= 'h0;
  else if (re_int == 1'b1)
  begin
    read_ptr <= #tQ read_ptr + 1'b1;
  end
end

// -----------------------------------------------------------------------------
// Write Address Counter
// -----------------------------------------------------------------------------
always @(posedge cp or negedge nreseta)
begin
  if (nreseta == 1'b0)
    write_ptr <= 'h0;
  else if (we_int == 1'b1)
  begin
    write_ptr <= write_ptr + 1'b1;
  end
end



// -----------------------------------------------------------------------------
// Last operation state saved
// -----------------------------------------------------------------------------
always @(posedge cp or negedge nreseta)
begin
  if (nreseta == 1'b0)
  begin
    readl <= 1'b1;
    writel <= 1'b0;
  end
  else 
  begin
    if (nrd == 1'b0 && nwr == 1'b0)
    begin
      if (fl == 1'b1)
      begin
        readl <= #tQ 1'b0;
        writel <= #tQ 1'b1;
      end
      else if (mt == 1'b1)
      begin
        readl <= #tQ 1'b0;
        writel <= #tQ 1'b1;
      end
      else 
      begin
        readl <= #tQ readl;
        writel <= #tQ writel;
      end
    end
    else if (nrd == 1'b0)
    begin
      readl <= #tQ 1'b1;
      writel <= #tQ 1'b0;
    end
    else if (nwr == 1'b0)
    begin
      readl <= #tQ 1'b0;
      writel <= #tQ 1'b1;
    end
    else
    begin
      readl <= #tQ readl;
      writel <= #tQ writel;
    end
  end
end


 
// -----------------------------------------------------------------------------
// FIFO RAM write
// -----------------------------------------------------------------------------
always @(posedge cp)
begin
  if (dfweb == 1'b0)
    ram_data[write_ptr] <= #tQ di;
end

assign dataout = ramout;


endmodule 

// -----------------------------------------------------------------------------
// Verilog Component Instantiation:
// -----------------------------------------------------------------------------
/*
   spi_fifo u1 (.cp(),         // FIFO clock
                .nrd(),        // FIFO Read enable
                .nwr(),        // FIFO Write enable
                .nreseta(),    // FIFO asynchronous reset
                .di(),         // FIFO Data input
                .full(),       // FIFO Full flag
                .empty(),      // FIFO Empty flag
                .level(),      // FIFO Real time level indicator bus
                .do());        // FIFO Data output bus

*/
// -----------------------------------------------------------------------------