spi_comp3_se.v

verilog语言写的SPI接口,全同步设计,低门数,可以很容易应用到嵌入设计方案中.

// HDLi Version 3.0a (beta) IP Bundle 1999.02.18
// Parameters: compare -b 4     -le -S 0 -p 0   -l vsc983 -Synopsys -rtl -nentity -nadd_p -ntiming -verilog -br 0,4,8,12,32,0  
// spi_comp3_se: 13.67 physical gates (vsc983)
// spi_comp3_se: 354.38 squm area (vsc983)
// -----------------------------------------------------------------------------
//                            VLSI Technology, Inc.
// -----------------------------------------------------------------------------
// Copyright 1999 by VLSI Technology, Inc. All rights reserved.
// 
// This module is property of VLSI Technology, Inc (VLSI) and its use is
// granted to the customer for the sole purpose of implementing in silicon
// provided by VLSI. This module may only be used in accordance with the
// provisions of the Design Integrator License Agreement.
// 
// -----------------------------------------------------------------------------
//                        Comparator Compiler Version 1.0a
// -----------------------------------------------------------------------------
// spi_comp3_se : structural Verilog
// "spi_comp3_se_rtl.v" contains the RTL Verilog
//
// Compiled by coste on Tue Jul 27 15:11:35 1999
// -----------------------------------------------------------------------------

module spi_comp3_se (
                     a,
                     b,
                     aleb);

   input  [3:0] a;
   input  [3:0] b;
   output       aleb;

   supply1 vdd;
   supply0 vss;


   wire   n000004;
   assign n000004 = a[3];
   wire   n000003;
   assign n000003 = a[2];
   wire   n000002;
   assign n000002 = a[1];
   wire   n000001;
   assign n000001 = a[0];
   wire   n000008;
   assign n000008 = b[3];
   wire   n000007;
   assign n000007 = b[2];
   wire   n000006;
   assign n000006 = b[1];
   wire   n000005;
   assign n000005 = b[0];
   wire   n000009;
   assign aleb = n000009;

   cg01d1  u000001(
                   .a(n000013),
                   .b(n000008),
                   .ci(n000015),
                   .co(n000009));
   cg01d1  u000002(
                   .a(n000012),
                   .b(n000007),
                   .ci(n000016),
                   .co(n000015));
   cg01d1  u000003(
                   .a(n000011),
                   .b(n000006),
                   .ci(n000017),
                   .co(n000016));
   fn01d1  u000004(
                   .a1(n000005),
                   .b1(n000001),
                   .zn(n000017));
   in01d1  u000005(
                   .i(n000004),
                   .zn(n000013));
   in01d1  u000006(
                   .i(n000003),
                   .zn(n000012));
   in01d1  u000007(
                   .i(n000002),
                   .zn(n000011));

endmodule // spi_comp3_se

// -----------------------------------------------------------------------------
// Verilog Component Instantiation:
// -----------------------------------------------------------------------------
/*
   spi_comp3_se u1 (.a(),        //  4 bit Source Operand
                    .b(),        //  4 bit Source Operand
                    .aleb());    // A <= B

*/
// -----------------------------------------------------------------------------
// Verilog Synthesis Commands:
// -----------------------------------------------------------------------------
/*
   set_dont_touch find(design, spi_comp3_se, -hierarchy)
   remove_attribute find(design, spi_comp3_se, -hierarchy) dont_touch
   set_ungroup find(design, spi_comp3_se, -hierarchy)
*/
// -----------------------------------------------------------------------------