spi_waitcounter_rtl.v

verilog语言写的SPI接口,全同步设计,低门数,可以很容易应用到嵌入设计方案中.

// HDLi Version 3.0 (beta)
// Parameters: counter -b3 -t0 -p1 -f0 -L0 -C  -R -S  -M   -l vsc983 -Synopsys -rtl -nentity -nadd_p -ntiming -verilog -br 0,4,8,12,32,0  
// spi_waitcounter: 39.00 physical gates (vsc983)
// spi_waitcounter: 1011.27 squm area (vsc983)
// -----------------------------------------------------------------------------
//                            VLSI Technology, Inc.
// -----------------------------------------------------------------------------
// Copyright 1999 by VLSI Technology, Inc. All rights reserved.
// 
// This module is property of VLSI Technology, Inc (VLSI) and its use is
// granted to the customer for the sole purpose of implementing in silicon
// provided by VLSI. This module may only be used in accordance with the
// provisions of the Design Integrator License Agreement.
// 
// -----------------------------------------------------------------------------
//                          Counter Compiler Version 1.1b
// -----------------------------------------------------------------------------
// spi_waitcounter : RTL Verilog
// (RTL is optimized for simulation, not synthesis)
// "spi_waitcounter.v" contains the Structural Verilog
//
// Compiled by coste_e on Fri Jun 18 10:46:07 1999
// -----------------------------------------------------------------------------
module spi_waitcounter (
                        clk,
                        cdn,
                        csn,
                        maxval,
                        q,
                        tci);

   input        clk;
   input        cdn;
   input        csn;
   input  [2:0] maxval;
   output [2:0] q;
   output       tci;


   parameter areset_value = 3'b000;
   parameter sreset_value = 3'b000;
   parameter minval = 3'b000;

   reg [2:0] q;
   wire tci;

   always @(posedge clk or negedge cdn)
   begin
      if (~cdn)
         q <= areset_value;
      else if (~csn)
         q <= sreset_value;
      else
         q <= ((q <= minval || q >= maxval) && &(q | ~maxval)) ? minval : (q+1);
   end

   assign tci = ((q <= minval || q>= maxval) && &(q | ~maxval));

endmodule // spi_waitcounter

// -----------------------------------------------------------------------------
// Verilog Component Instantiation:
// -----------------------------------------------------------------------------
/*
   spi_waitcounter u1 (.clk(),       // Clock Input
                       .cdn(),       // Clear Direct Not Input
                       .csn(),       // Clear Synchronous Not Input
                       .maxval(),    // Programmable Maximum Count Value
                       .q(),         //  3 bit Result
                       .tci());      // Terminal Count Indicator

*/
// -----------------------------------------------------------------------------
// Verilog Synthesis Commands:
// -----------------------------------------------------------------------------
/*
   set_dont_touch find(design, spi_waitcounter, -hierarchy)
   remove_attribute find(design, spi_waitcounter, -hierarchy) dont_touch
   set_ungroup find(design, spi_waitcounter, -hierarchy)
*/
// -----------------------------------------------------------------------------