spi_clkdiv_count_rtl.v

verilog语言写的SPI接口,全同步设计,低门数,可以很容易应用到嵌入设计方案中.

// HDLi Version 3.0d IP Bundle 1999.08.25
// Parameters: counter -b4 -t0 -p1 -f0 -L0 -C  -R   -M   -l vsc983 -padlib vst8p31 -Synopsys -rtl -nentity -nadd_p -ntiming -verilog -br 0,4,8,12,32,0  
// spi_clkdiv_count: 51.00 physical gates (vsc983)
// spi_clkdiv_count: 1322.43 squm area (vsc983)
// -----------------------------------------------------------------------------
//                            VLSI Technology, Inc.
// -----------------------------------------------------------------------------
// Copyright 1999 by VLSI Technology, Inc. All rights reserved.
// 
// This module is property of VLSI Technology, Inc (VLSI) and its use is
// granted to the customer for the sole purpose of implementing in silicon
// provided by VLSI. This module may only be used in accordance with the
// provisions of the Design Integrator License Agreement.
// 
// -----------------------------------------------------------------------------
//                          Counter Compiler Version 1.1b
// -----------------------------------------------------------------------------
// spi_clkdiv_count : RTL Verilog
// (RTL is optimized for simulation, not synthesis)
// "spi_clkdiv_count.v" contains the Structural Verilog
//
// Compiled by coste on Wed Oct 27 16:04:09 1999
// -----------------------------------------------------------------------------
module spi_clkdiv_count (
                         clk,
                         cdn,
                         maxval,
                         q,
                         tci);

   input        clk;
   input        cdn;
   input  [3:0] maxval;
   output [3:0] q;
   output       tci;


   parameter areset_value = 4'b0000;
   parameter minval = 4'b0000;

   reg [3:0] q;
   wire tci;

   always @(posedge clk or negedge cdn)
   begin
      if (~cdn)
         q <= areset_value;
      else
         q <= ((q <= minval || q >= maxval) && &(q | ~maxval)) ? minval : (q+1);
   end

   assign tci = ((q <= minval || q>= maxval) && &(q | ~maxval));

endmodule // spi_clkdiv_count

// -----------------------------------------------------------------------------
// Verilog Component Instantiation:
// -----------------------------------------------------------------------------
/*
   spi_clkdiv_count u1 (.clk(),       // Clock Input
                        .cdn(),       // Clear Direct Not Input
                        .maxval(),    // Programmable Maximum Count Value
                        .q(),         //  4 bit Result
                        .tci());      // Terminal Count Indicator

*/
// -----------------------------------------------------------------------------
// Verilog Synthesis Commands:
// -----------------------------------------------------------------------------
/*
   set_dont_touch find(design, spi_clkdiv_count, -hierarchy)
   remove_attribute find(design, spi_clkdiv_count, -hierarchy) dont_touch
   set_ungroup find(design, spi_clkdiv_count, -hierarchy)
*/
// -----------------------------------------------------------------------------