fir1.v

FIR滤波器的verilog实现

module	FIR1(clock,data_in,d_first,d_second,d_three,d_four,d_five,d_six, o_first,o_second,o_third,o_four,o_five,o_six,
            data_out,dout_1,dout_2,dout_3,dout_4);

output  [10:0]	 o_first,o_six;
reg		[10:0]   o_first,o_six;
output  [13:0]   o_second,o_five;
reg		[13:0]	 o_second,o_five;
output  [14:0]   o_third,o_four;
reg		[14:0]	 o_third,o_four;

output	[7:0]	 data_out;
reg		[7:0]	 data_out;

reg		[10:0]	 c_first,c_six;
reg		[13:0]	 c_second,c_five;
reg		[14:0]	 c_third,c_four;

output  [7:0]    d_first,d_second,d_three,d_four,d_five,d_six;//D触发器构成Z(-1);
reg	    [7:0]    d_first,d_second,d_three,d_four,d_five,d_six;
reg		[7:0]	 b_first,b_second,b_three,b_four,b_five,b_six;	
reg		[15:0]	 dout_1,dout_2,dout_3,dout_4;
output		[15:0]	 dout_1,dout_2,dout_3,dout_4;

input			clock;
input	[7:0]   data_in;


always @(posedge clock)

	begin
		
		b_first<=data_in;
		d_first<=data_in;
		b_second<=d_first;
		d_second<=d_first;
		b_three<=d_second;
		d_three<=d_second;
		b_four<=d_three;
		d_four<=d_three;
		b_five<=d_four;
		d_five<=d_four;
		b_six<=d_five;
	    d_six<=d_five;
		
		end

always @(posedge clock)

	begin 
	    c_first=(b_first<<2)+b_first;
	    o_first<=c_first;
	end
	
always @(posedge clock)

	begin 
	    c_six=(b_six<<2)+b_six;
	    o_six<=c_six;
	end
	
always @(posedge clock)

	begin 
	    c_second=(b_second<<5)+(b_second<<1);
	    o_second<=c_second;
	end	
	
always @(posedge clock)

	begin 
	    c_five=(b_five<<5)+(b_five<<1);
	    o_five<=c_five;
	end
	
	always @(posedge clock)

	begin 
	    c_third=(b_three<<6)+(b_three<<4)+(b_three<<3)+b_three;
	    o_third<=c_third;
	end
	
	always @(posedge clock)

	begin 
	    c_four=(b_four<<6)+(b_four<<4)+(b_four<<3)+(b_four<<0);
	    o_four<=c_four;
	end
	


always @(posedge clock)

	begin 
     dout_1=c_first+c_six;
	end

	
always @(posedge clock)

	begin 
     dout_2=c_second+c_five;
	end
	

	
always @(posedge clock)

	begin 
     dout_3=c_third+c_four;
	end
	

	
always @(posedge clock)

	begin 
     dout_4=dout_1+dout_2+dout_3;
	end
	





always @(posedge clock)

	begin 
      
	  data_out<=dout_4>>8;
  
	end
	
	endmodule