pluse_delay.vhd

利用VHDL语言实现单稳触发电路

library ieee;
use ieee.std_logic_1164.all;

entity pluse_delay is
	port(square:in std_logic;
		 clk:in std_logic;
		 out_up:out std_logic;
		 out_down:out std_logic);
end pluse_delay;

architecture pluse_delay of pluse_delay is
	signal not_square:std_logic;
	signal finish1:std_logic;
	signal finish2:std_logic;
	signal en_count1:std_logic;
	signal en_count2:std_logic;
begin
	
	process(square)
	begin
		not_square<=not square;
		if finish1='1' then 
			out_up<='0';
			en_count1<='0';
		elsif square'event and square='1' then 
			out_up<='1';
			en_count1<='1';
		end if;
	end process;

	process(not_square)
	begin
		if finish2='1' then 
			out_down<='0';
			en_count2<='0';
		elsif not_square'event and not_square='1' then 
			out_down<='1';
			en_count2<='1';
		end if;
	end process;
	
	process(clk)	
		variable cnt:integer;
	begin
		if clk'event and clk='1' then 
			if en_count1='1' then 
				if cnt=1 then 
					cnt:=0;
					finish1<='1';
				else
					cnt:=cnt+1;
				end if;
			else
				finish1<='0';
			end if;
	    end if;
	end process;

	process(clk)	
		variable cnt:integer;
	begin
		if clk'event and clk='1' then 
			if en_count2='1' then 
				if cnt=1 then 
					cnt:=0;
					finish2<='1';
				else
					cnt:=cnt+1;
				end if;
			else
				finish2<='0';
			end if;
	    end if;
	end process;

end pluse_delay;