📄 pluse_delay.rpt
字号:
68 - - A -- OUTPUT 0 1 0 0 out_up
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: e:\pluse_delay\pluse_delay.rpt
pluse_delay
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 5 - A 02 AND2 0 2 0 1 |LPM_ADD_SUB:232|addcore:adder|:167
- 7 - A 02 AND2 0 3 0 1 |LPM_ADD_SUB:232|addcore:adder|:171
- 2 - A 02 AND2 0 4 0 2 |LPM_ADD_SUB:232|addcore:adder|:175
- 5 - A 10 AND2 0 2 0 2 |LPM_ADD_SUB:232|addcore:adder|:179
- 7 - A 10 AND2 0 2 0 2 |LPM_ADD_SUB:232|addcore:adder|:183
- 2 - A 10 AND2 0 2 0 2 |LPM_ADD_SUB:232|addcore:adder|:187
- 4 - A 03 AND2 0 2 0 2 |LPM_ADD_SUB:232|addcore:adder|:191
- 2 - A 03 AND2 0 2 0 4 |LPM_ADD_SUB:232|addcore:adder|:195
- 5 - A 08 AND2 0 2 0 1 |LPM_ADD_SUB:232|addcore:adder|:199
- 7 - A 08 AND2 0 3 0 1 |LPM_ADD_SUB:232|addcore:adder|:203
- 2 - A 08 AND2 0 4 0 2 |LPM_ADD_SUB:232|addcore:adder|:207
- 3 - A 07 AND2 0 2 0 4 |LPM_ADD_SUB:232|addcore:adder|:211
- 5 - A 07 AND2 0 2 0 1 |LPM_ADD_SUB:232|addcore:adder|:215
- 7 - A 07 AND2 0 3 0 1 |LPM_ADD_SUB:232|addcore:adder|:219
- 1 - A 07 AND2 0 4 0 2 |LPM_ADD_SUB:232|addcore:adder|:223
- 3 - A 06 AND2 0 2 0 4 |LPM_ADD_SUB:232|addcore:adder|:227
- 5 - A 06 AND2 0 2 0 1 |LPM_ADD_SUB:232|addcore:adder|:231
- 7 - A 06 AND2 0 3 0 1 |LPM_ADD_SUB:232|addcore:adder|:235
- 2 - A 06 AND2 0 4 0 2 |LPM_ADD_SUB:232|addcore:adder|:239
- 8 - A 11 AND2 0 2 0 2 |LPM_ADD_SUB:232|addcore:adder|:243
- 5 - A 01 AND2 0 2 0 2 |LPM_ADD_SUB:232|addcore:adder|:247
- 7 - A 01 AND2 0 2 0 2 |LPM_ADD_SUB:232|addcore:adder|:251
- 2 - A 01 AND2 0 2 0 2 |LPM_ADD_SUB:232|addcore:adder|:255
- 1 - A 12 AND2 0 2 0 4 |LPM_ADD_SUB:232|addcore:adder|:259
- 4 - A 12 AND2 0 2 0 1 |LPM_ADD_SUB:232|addcore:adder|:263
- 6 - A 12 AND2 0 3 0 1 |LPM_ADD_SUB:232|addcore:adder|:267
- 2 - A 12 AND2 0 4 0 2 |LPM_ADD_SUB:232|addcore:adder|:271
- 3 - A 04 AND2 0 2 0 2 |LPM_ADD_SUB:232|addcore:adder|:275
- 5 - A 04 AND2 0 2 0 2 |LPM_ADD_SUB:232|addcore:adder|:279
- 7 - A 04 AND2 0 2 0 1 |LPM_ADD_SUB:232|addcore:adder|:283
- 4 - B 15 AND2 0 2 0 1 |LPM_ADD_SUB:863|addcore:adder|:167
- 7 - B 15 AND2 0 3 0 1 |LPM_ADD_SUB:863|addcore:adder|:171
- 2 - B 15 AND2 0 4 0 2 |LPM_ADD_SUB:863|addcore:adder|:175
- 4 - B 23 AND2 0 2 0 2 |LPM_ADD_SUB:863|addcore:adder|:179
- 6 - B 23 AND2 0 2 0 2 |LPM_ADD_SUB:863|addcore:adder|:183
- 1 - B 23 AND2 0 2 0 2 |LPM_ADD_SUB:863|addcore:adder|:187
- 1 - B 22 AND2 0 2 0 2 |LPM_ADD_SUB:863|addcore:adder|:191
- 2 - B 22 AND2 0 2 0 4 |LPM_ADD_SUB:863|addcore:adder|:195
- 5 - B 20 AND2 0 2 0 1 |LPM_ADD_SUB:863|addcore:adder|:199
- 7 - B 20 AND2 0 3 0 1 |LPM_ADD_SUB:863|addcore:adder|:203
- 2 - B 20 AND2 0 4 0 2 |LPM_ADD_SUB:863|addcore:adder|:207
- 2 - B 16 AND2 0 2 0 4 |LPM_ADD_SUB:863|addcore:adder|:211
- 4 - B 21 AND2 0 2 0 1 |LPM_ADD_SUB:863|addcore:adder|:215
- 6 - B 21 AND2 0 3 0 1 |LPM_ADD_SUB:863|addcore:adder|:219
- 2 - B 21 AND2 0 4 0 2 |LPM_ADD_SUB:863|addcore:adder|:223
- 1 - B 19 AND2 0 2 0 4 |LPM_ADD_SUB:863|addcore:adder|:227
- 5 - B 19 AND2 0 2 0 1 |LPM_ADD_SUB:863|addcore:adder|:231
- 7 - B 19 AND2 0 3 0 1 |LPM_ADD_SUB:863|addcore:adder|:235
- 2 - B 19 AND2 0 4 0 2 |LPM_ADD_SUB:863|addcore:adder|:239
- 2 - B 17 AND2 0 2 0 2 |LPM_ADD_SUB:863|addcore:adder|:243
- 5 - B 14 AND2 0 2 0 2 |LPM_ADD_SUB:863|addcore:adder|:247
- 7 - B 14 AND2 0 2 0 2 |LPM_ADD_SUB:863|addcore:adder|:251
- 2 - B 14 AND2 0 2 0 2 |LPM_ADD_SUB:863|addcore:adder|:255
- 1 - B 13 AND2 0 2 0 4 |LPM_ADD_SUB:863|addcore:adder|:259
- 5 - B 13 AND2 0 2 0 1 |LPM_ADD_SUB:863|addcore:adder|:263
- 7 - B 13 AND2 0 3 0 1 |LPM_ADD_SUB:863|addcore:adder|:267
- 2 - B 13 AND2 0 4 0 2 |LPM_ADD_SUB:863|addcore:adder|:271
- 3 - B 18 AND2 0 2 0 2 |LPM_ADD_SUB:863|addcore:adder|:275
- 5 - B 18 AND2 0 2 0 2 |LPM_ADD_SUB:863|addcore:adder|:279
- 7 - B 18 AND2 0 2 0 1 |LPM_ADD_SUB:863|addcore:adder|:283
- 7 - A 11 DFFE + 0 1 1 0 :3
- 7 - B 17 DFFE + 0 1 1 0 :5
- 6 - A 11 DFFE + 0 3 0 2 finish1 (:8)
- 3 - A 11 DFFE + 0 1 0 34 en_count1 (:9)
- 6 - B 17 DFFE + 0 3 0 2 finish2 (:10)
- 4 - B 17 DFFE + 0 1 0 34 en_count2 (:11)
- 8 - A 04 DFFE + 0 3 0 1 cnt31 (:60)
- 6 - A 04 DFFE + 0 3 0 2 cnt30 (:61)
- 4 - A 04 DFFE + 0 3 0 2 cnt29 (:62)
- 2 - A 04 DFFE + 0 3 0 2 cnt28 (:63)
- 7 - A 12 DFFE + 0 3 0 2 cnt27 (:64)
- 5 - A 12 DFFE + 0 3 0 3 cnt26 (:65)
- 3 - A 12 DFFE + 0 3 0 4 cnt25 (:66)
- 1 - A 01 DFFE + 0 3 0 2 cnt24 (:67)
- 8 - A 01 DFFE + 0 3 0 2 cnt23 (:68)
- 6 - A 01 DFFE + 0 3 0 2 cnt22 (:69)
- 3 - A 01 DFFE + 0 3 0 2 cnt21 (:70)
- 2 - A 11 DFFE + 0 3 0 2 cnt20 (:71)
- 8 - A 06 DFFE + 0 3 0 2 cnt19 (:72)
- 6 - A 06 DFFE + 0 3 0 3 cnt18 (:73)
- 4 - A 06 DFFE + 0 3 0 4 cnt17 (:74)
- 1 - A 03 DFFE + 0 3 0 2 cnt16 (:75)
- 8 - A 07 DFFE + 0 3 0 2 cnt15 (:76)
- 6 - A 07 DFFE + 0 3 0 3 cnt14 (:77)
- 4 - A 07 DFFE + 0 3 0 4 cnt13 (:78)
- 1 - A 08 DFFE + 0 3 0 2 cnt12 (:79)
- 8 - A 08 DFFE + 0 3 0 2 cnt11 (:80)
- 6 - A 08 DFFE + 0 3 0 3 cnt10 (:81)
- 4 - A 08 DFFE + 0 3 0 4 cnt9 (:82)
- 3 - A 03 DFFE + 0 3 0 2 cnt8 (:83)
- 1 - A 10 DFFE + 0 3 0 2 cnt7 (:84)
- 8 - A 10 DFFE + 0 3 0 2 cnt6 (:85)
- 6 - A 10 DFFE + 0 3 0 2 cnt5 (:86)
- 4 - A 10 DFFE + 0 3 0 2 cnt4 (:87)
- 8 - A 02 DFFE + 0 3 0 2 cnt3 (:88)
- 6 - A 02 DFFE + 0 3 0 3 cnt2 (:89)
- 4 - A 02 DFFE + 0 3 0 4 cnt1 (:90)
- 3 - A 02 DFFE + 0 1 0 6 cnt0 (:91)
- 3 - A 10 OR2 s 0 4 0 1 ~162~1
- 1 - A 02 OR2 s 0 4 0 1 ~162~2
- 4 - A 01 OR2 s 0 4 0 1 ~162~3
- 1 - A 06 OR2 s 0 4 0 1 ~162~4
- 2 - A 07 OR2 s 0 4 0 1 ~162~5
- 3 - A 08 OR2 s 0 4 0 1 ~162~6
- 4 - A 11 OR2 s 0 4 0 1 ~162~7
- 1 - A 04 OR2 s 0 4 0 1 ~162~8
- 8 - A 12 OR2 s 0 4 0 1 ~162~9
- 5 - A 11 OR2 s 0 4 0 2 ~162~10
- 1 - A 11 OR2 s 0 3 0 31 ~636~1
- 8 - B 18 DFFE + 0 3 0 1 cnt31~345 (:691)
- 6 - B 18 DFFE + 0 3 0 2 cnt30~345 (:692)
- 4 - B 18 DFFE + 0 3 0 2 cnt29~345 (:693)
- 1 - B 18 DFFE + 0 3 0 2 cnt28~345 (:694)
- 8 - B 13 DFFE + 0 3 0 2 cnt27~345 (:695)
- 6 - B 13 DFFE + 0 3 0 3 cnt26~345 (:696)
- 3 - B 13 DFFE + 0 3 0 4 cnt25~345 (:697)
- 3 - B 14 DFFE + 0 3 0 2 cnt24~345 (:698)
- 8 - B 14 DFFE + 0 3 0 2 cnt23~345 (:699)
- 6 - B 14 DFFE + 0 3 0 2 cnt22~345 (:700)
- 4 - B 14 DFFE + 0 3 0 2 cnt21~345 (:701)
- 3 - B 17 DFFE + 0 3 0 2 cnt20~345 (:702)
- 8 - B 19 DFFE + 0 3 0 2 cnt19~345 (:703)
- 6 - B 19 DFFE + 0 3 0 3 cnt18~345 (:704)
- 3 - B 19 DFFE + 0 3 0 4 cnt17~345 (:705)
- 8 - B 21 DFFE + 0 3 0 2 cnt16~345 (:706)
- 7 - B 21 DFFE + 0 3 0 2 cnt15~345 (:707)
- 5 - B 21 DFFE + 0 3 0 3 cnt14~345 (:708)
- 3 - B 21 DFFE + 0 3 0 4 cnt13~345 (:709)
- 4 - B 16 DFFE + 0 3 0 2 cnt12~345 (:710)
- 8 - B 20 DFFE + 0 3 0 2 cnt11~345 (:711)
- 6 - B 20 DFFE + 0 3 0 3 cnt10~345 (:712)
- 4 - B 20 DFFE + 0 3 0 4 cnt9~345 (:713)
- 8 - B 22 DFFE + 0 3 0 2 cnt8~345 (:714)
- 8 - B 23 DFFE + 0 3 0 2 cnt7~345 (:715)
- 7 - B 23 DFFE + 0 3 0 2 cnt6~345 (:716)
- 5 - B 23 DFFE + 0 3 0 2 cnt5~345 (:717)
- 3 - B 23 DFFE + 0 3 0 2 cnt4~345 (:718)
- 8 - B 15 DFFE + 0 3 0 2 cnt3~345 (:719)
- 6 - B 15 DFFE + 0 3 0 3 cnt2~345 (:720)
- 3 - B 15 DFFE + 0 3 0 4 cnt1~345 (:721)
- 5 - B 15 DFFE + 0 1 0 6 cnt0~345 (:722)
- 2 - B 23 OR2 s 0 4 0 1 ~793~1
- 1 - B 15 OR2 s 0 4 0 1 ~793~2
- 1 - B 14 OR2 s 0 4 0 1 ~793~3
- 4 - B 19 OR2 s 0 4 0 1 ~793~4
- 1 - B 21 OR2 s 0 4 0 1 ~793~5
- 3 - B 20 OR2 s 0 4 0 1 ~793~6
- 1 - B 20 OR2 s 0 4 0 1 ~793~7
- 2 - B 18 OR2 s 0 4 0 1 ~793~8
- 4 - B 13 OR2 s 0 4 0 1 ~793~9
- 5 - B 17 OR2 s 0 4 0 2 ~793~10
- 1 - B 17 OR2 s 0 3 0 31 ~1267~1
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
p = Packed register
Device-Specific Information: e:\pluse_delay\pluse_delay.rpt
pluse_delay
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 24/ 96( 25%) 4/ 48( 8%) 0/ 48( 0%) 0/16( 0%) 1/16( 6%) 0/16( 0%)
B: 26/ 96( 27%) 0/ 48( 0%) 2/ 48( 4%) 0/16( 0%) 1/16( 6%) 0/16( 0%)
C: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: e:\pluse_delay\pluse_delay.rpt
pluse_delay
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 66 clk
INPUT 4 square
Device-Specific Information: e:\pluse_delay\pluse_delay.rpt
pluse_delay
** CLEAR SIGNALS **
Type Fan-out Name
DFF 3 finish1
DFF 3 finish2
Device-Specific Information: e:\pluse_delay\pluse_delay.rpt
pluse_delay
** EQUATIONS **
clk : INPUT;
square : INPUT;
-- Node name is ':722' = 'cnt0~345'
-- Equation name is 'cnt0~345', location is LC5_B15, type is buried.
cnt0~345 = DFFE( _EQ001, GLOBAL( clk), VCC, VCC, VCC);
_EQ001 = cnt0~345 & !en_count2
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