cnt10.vhd

来自「在Xilinx环境下编写的vhdl程序」· VHDL 代码 · 共 39 行

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY cnt10 IS
	port (
	Q: OUT std_logic_VECTOR(3 downto 0);
	CLK: IN std_logic;
	ACLR: IN std_logic);

END cnt10;

ARCHITECTURE cnt10_a OF cnt10 IS
	signal  count : std_logic_vector(3 downto 0):="0000";	--count
	signal  reset : std_logic;
	signal  clk_in: std_logic;



BEGIN

Q<=count;
reset<=ACLR;
clk_in<=CLK;

process (clk_in, reset,count) 
begin
   if reset='1' then 
      count <= (others => '0');
   elsif clk_in='1' and clk_in'event then
		if count="1001" then count<="0000";
		else
         count <= count + 1;
		end if;
   end if;
end process;

END cnt10_a;