keyboard.vhd

在Xilinx环境下编写的vhdl程序

library ieee;
use ieee.std_logic_1164.all;

entity keyboard is port(
kb_data : in std_logic;
kb_clk : in std_logic;
clk : in std_logic;
reset : in std_logic;
data : buffer std_logic_vector(7 downto 0);
data_ready : out std_logic
--rs : out std_logic_vector(6 downto 0)
);
end entity;

architecture behav of keyboard is

signal master, slave: std_logic_vector(9 downto 0);
signal clk_in : std_logic;

type status is (s0,makecode);
signal state : status;

signal counter : integer range 0 to 11;
signal data_in : std_logic;
signal data_in_delay : std_logic;

begin

process(clk,reset)
begin
	if reset='0' then
		clk_in<='0';
	elsif clk='1' and clk'event then
		clk_in<=kb_clk;
end if;		 
end process;

			 
masterp:
process(clk_in,reset)
begin
	if reset='0' then
	master<="0000000000"; 
	elsif (clk_in'event and clk_in='0') then
		master<=kb_data&slave(9 downto 1);
	end if;	 
end process masterp;


slavep:
process(reset,clk_in)
begin
	if reset='0' then
		slave<="0000000000";	  
	elsif (clk_in'event and clk_in='1') then
		slave<=master;
	end if;	 
end process slavep;


process(reset,clk_in)
variable counter_in : integer range 0 to 11;
begin
if reset='0' then
	counter_in:=0;
elsif clk_in'event and clk_in='0' then
	if master(9 downto 2)=X"F0" then
		counter_in:=10;
	elsif counter_in=11 then
		counter_in:=1;
	else
		counter_in:=counter_in+1;
	end if;
end if;
counter<=counter_in;
end process;


--state & data
process(clk_in,reset)
begin
if reset='0' then
	state<=makecode;
	data<="00000000";
	data_in<='0';
elsif clk_in'event and clk_in='1' then
	if counter=10 then
		case state is
		when makecode=> 
			if master(8 downto 1)=X"F0" then
				state<=s0;
			else
				data<= master(8 downto 1);
				data_in <= '1';
			end if;	 
		when s0=> 
			state<=makecode;
		end case;	  
	else
		data_in <= '0';
	end if;
end if;
end process;


--data_ready
data_ready <= data_in and (not data_in_delay);
process(clk,reset)
begin
if reset='0' then
	data_in_delay<='0';
elsif clk='1' and clk'event then
	data_in_delay<=data_in;	
end if;


end process;
--
--rs<="1000000" when data=X"45" else  --0
--	 "1111001" when data=X"16" else  --1
--	 "0100100" when data=X"1E" else --2	  
--	 "0110000" when data=X"26" else  --3
--	 "0011001" when data=X"25" else  --4
--	 "0010010" when data=X"2E" else  --5
--	 "0000010" when data=X"36" else  --6
--	 "1111000" when data=X"3D" else  --7
--	 "0000000" when data=X"3E" else  --8
--	 "0010000" when data=X"46" else  --9
--	 "0000000";
--
--

end behav;