📄 main.vhd
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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity main is
port(onoff :in std_logic;
crin :in std_logic;--100 my plane dye; 010 my plane eat bullet; 001 kill one enemy;
scain :in std_logic;
rest :in std_logic;
rst_sys :out std_logic;--
bullet_add :out std_logic;
score_add:out std_logic;
bullet_jian :out std_logic;
move_en :out std_logic;
rest_jian :out std_logic;
level_add :out std_logic;
en :out std_logic_vector(2 downto 0));
end main;
architecture behave of main is
begin
signal present_state,next_state :std_logic_vector(3 downto 0);
process(present_state,onoff)
begin
case present_state is
when"0000"=>if(onoff='1')then--stop
next_state<="0001";
else next_state<="0000";
end if;
when "0001"=>if(onoff='1')then--analize
next_state<="0000";
else next_state<="0010";
end if;
when "0010"=>if(onoff='1')then--mei ju analize
next_state<="0000";
else next_state<="0011";
end if;
when "0011"=>if(onoff='1')then--move
next_state<="0000";
else next_state<="0111";
end if;
when "0111"=>if(onoff='1')then--isor add score
next_state="0000";
else case crin is
when "100"=>next_state<="0100";
when"010"=>next_state<="0101";
when "001"=>next_state<="0110";
when others=>next_state<="0011";
end case;
end if;
when "0100"=>if(onoff='1')then--bei zhuang
next_state<="0000";
elsif
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