wan_dff.vhd

来自「此为一用VHDL编写的硬件游戏程序」· VHDL 代码 · 共 25 行

library ieee;
use ieee.std_logic_1164.all;

entity wan_dff is
port(d,clk,en :in std_logic;
     q ,qb :buffer std_logic);
end wan_dff;
architecture rtl1 of wan_dff is
begin
  qb<=not q;
  process(clk)
  begin
    if(rising_edge(clk))then
    if(en='1')then
    q<=d;
    
    else 
      q<=q;
      
    end if;
   end if; 
  end process;
end rtl1;