dff.vhd

来自「此为一用VHDL编写的硬件游戏程序」· VHDL 代码 · 共 27 行

library ieee;
use ieee.std_logic_1164.all;
entity dff is
port(d,clk : in std_logic;
     rst   :in std_logic;
     q :buffer std_logic;
     nq :out std_logic);
end dff;
architecture rtl of dff is
begin
  nq<=not q; 
  process(clk)
    
  begin
     if(rising_edge(clk))then
     if(rst='1')then
     q<='0';
     --nq<='1';
     else
     q<=d;
     --nq<=not d;
     end if;
     end if;
  end process;
end rtl;