m16add_jian.vhd

来自「此为一用VHDL编写的硬件游戏程序」· VHDL 代码 · 共 43 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity m16add_jian is
port(clk :in std_logic;
     add :in std_logic;
     jian :in std_logic;
     set  :in std_logic;
     win  :in std_logic_vector(3 downto 0);
     weizhi :buffer std_logic_vector(3 downto 0));
end m16add_jian;
architecture behave of m16add_jian is
signal temp :std_logic_vector(1 downto 0);
begin
    temp<=add&jian;
   process(clk)
   begin
      if(rising_edge(clk))then
         if(set='1')then
              weizhi<=win;
         else
            case temp is
               when "01"=>case weizhi is
                             when "0001"=>weizhi<="0011";
                             when "0010"=>weizhi<="0011";
                             when "0011"=>weizhi<="0011";
                             when "0000"=>weizhi<="0000";
                             when others=>weizhi<=weizhi-1;
                          end case;
                when "10"=>case weizhi is
                             when "0001"=>weizhi<="0011";
                             when "0010"=>weizhi<="0011";
                             when "0000"=>weizhi<="0000";
                             when "1111"=>weizhi<="1111";
                             when others=>weizhi<=weizhi+1;
                          end case;
                when others=>weizhi<=weizhi;
             end case;
         end if;
       end if;
end process;
end behave;