📄 wan_xiaoshi.vhd
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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity wan_xiaoshi is
port(inf :in std_logic_vector(15 downto 0);
sel :in std_logic_vector(3 downto 0);
infoout : out std_logic_vector(15 downto 0));
end wan_xiaoshi;
architecture behave of wan_xiaoshi is
begin
process(sel)
begin
case sel is
when "0000"=>infoout(15 downto 4)<=inf(15 downto 4);
infoout(3 downto 0)<="0000";
when"0001"=>infoout(15 downto 5)<=inf(15 downto 5);
infoout(4 downto 1)<="0000";
infoout(0)<=inf(0);
when "0010"=>infoout(15 downto 6)<=inf(15 downto 6);
infoout(5 downto 2)<="0000";
infoout(1 downto 0)<=inf(1 downto 0);
when "0011"=>infoout(15 downto 7)<=inf(15 downto 7);
infoout(6 downto 3)<="0000";
infoout(2 downto 0)<=inf(2 downto 0);
when "0100"=>infoout(15 downto 8)<=inf(15 downto 8);
infoout(7 downto 4)<="0000";
infoout(3 downto 0)<=inf(3 downto 0);
when "0101"=>infoout(15 downto 9)<=inf(15 downto 9);
infoout(8 downto 5)<="0000";
infoout(4 downto 0)<=inf(4 downto 0);
when "0110"=>infoout(15 downto 10)<=inf(15 downto 10);
infoout(9 downto 6)<="0000";
infoout(5 downto 0)<=inf(5 downto 0);
when "0111"=>infoout(15 downto 11)<=inf(15 downto 11);
infoout(10 downto 7)<="0000";
infoout(6 downto 0)<=inf(6 downto 0);
when "1000"=>infoout(15 downto 12)<=inf(15 downto 12);
infoout(11 downto 8)<="0000";
infoout(7 downto 0)<=inf(7 downto 0);
when "1001"=>infoout(15 downto 13)<=inf(15 downto 13);
infoout(12 downto 9)<="0000";
infoout(8 downto 0)<=inf(8 downto 0);
when "1010"=>infoout(15 downto 14)<=inf(15 downto 14);
infoout(13 downto 10)<="0000";
infoout(9 downto 0)<=inf(9 downto 0);
when "1011"=>infoout(15)<=inf(15);
infoout(14 downto 11)<="0000";
infoout(10 downto 0)<=inf(10 downto 0);
when "1100"=>infoout(15 downto 12)<="0000";
infoout(11 downto 0)<=inf(11 downto 0);
when "1101"=>infoout(15 downto 13)<="000";
infoout(12 downto 0)<=inf(12 downto 0);
when "1110"=>infoout(15 downto 14)<="00";
infoout(13 downto 0)<=inf(13 downto 0);
when "1111"=>infoout(15)<='0';
infoout(14 downto 0)<=inf(14 downto 0);
when others=>infoout(15 downto 0)<=inf(15 downto 0);
end case;
end process;
end behave;
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