piso.map.summary

FPGA数字移相器,编程环境为QUIRTE2,编程语言采用硬件描述语言vhdl

Flow Status : Successful - Sun Aug 28 21:18:26 2005
Quartus II Version : 4.1 Build 181 06/29/2004 SJ Full Version
Revision Name : piso
Top-level Entity Name : top
Family : Cyclone
Device : EP1C3T144C8
Timing Models : Production
Total logic elements : 471
Total pins : 34
Total memory bits : 8,192
Total PLLs : 0